PDF STK25C48 Data sheet ( Hoja de datos )

Número de pieza	STK25C48
Descripción	CMOS Nonvolatile Static RAM
Fabricantes	Simtek
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No Preview Available ! www.DataSheet4U.com STK25C48 2K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs FEATURES • Nonvolatile Storage without Battery Problems • Directly Replaces 2K x 8 Static RAM, Battery- Backed RAM or EEPROMs • 25ns, 35ns and 45ns Access Times • STORE to Nonvolatile Elements Initiated by AutoStore™ on Power Down • RECALL to SRAM Initiated by Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to Nonvolatile Ele- ments • 100-Year Data Retention over Full Industrial Temperature Range • Commercial and Industrial Temperatures • 24-Pin 600 PDIP Package DESCRIPTION The STK25C48 is a fast SRAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in the Nonvolatile Elements. Data transfers from the SRAM to the Nonvola- tile Elements (the STORE operation) can take place auto- matically on power down using charge stored in system capacitance. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automati- cally on restoration of power. The nvSRAM can be used in place of existing 2K x 8 SRAMs and also matches the pinout of 2K x 8 battery-backed SRAMs, EPROMs and EEPROMs, allowing direct substitution while enhancing performance. No support circuitry is required for micro- processor interfacing. BLOCK DIAGRAM QUANTUM TRAP 32 x 512 A5 STORE A6 STATIC RAM A7 ARRAY RECALL A8 32 x 512 A9 STORE/ RECALL CONTROL VCC POWER CONTROL DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 G E W PIN CONFIGURATIONS 1 24 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 PIN NAMES VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 24 - 600 PDIP A0 - A10 W DQ0 - DQ7 E G VCC VSS Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 5V) Ground March 2006 1 Document Control # ML0005 rev 0.2 1 page AutoStore™/POWER-UP RECALL SYMBOLS NO. Standard PARAMETER 22 tRESTORE 23 tSTORE 24 tDELAY 25 VSWITCH 26 VRESET Power-up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level Note k: tRESTORE starts from the time VCC rises above VSWITCH. AutoStore™/POWER-UP RECALL VCC 25 5V VSWITCH 26 VRESET AutoStore™ POWER-UP RECALL W 22 tRESTORE DQ (DATA OUT) 24 tDELAY STK25C48 (VCC = 5.0V ± 10%) STK25C48 MIN MAX UNITS NOTES 550 μs 10 ms k g 1 μs 4.0 4.5 V g 3.6 V e 23 tSTORE POWER-UP BROWN OUT RECALL NO STORE DUE TO NO SRAM WRITES NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStore™ NO RECALL (VCC DID NOT GO BELOW VRESET) BROWN OUT AutoStore™ RECALL WHEN VCC RETURNS ABOVE VSWITCH March 2006 5 Document Control # ML0005 rev 0.2 5 Page

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Número de pieza	Descripción	Fabricantes
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