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PDF STK22C48 Data sheet ( Hoja de datos )

Número de pieza STK22C48
Descripción 2Kx8 AutoStore nvSRAM
Fabricantes Simtek 
Logotipo Simtek Logotipo



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No Preview Available ! STK22C48 Hoja de datos, Descripción, Manual

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FEATURES
• 25, 45 ns Read Access & R/W Cycle Times
• Unlimited Read/Write Endurance
• Automatic Non-Volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5V + 10% Operation
• Commercial, Industrial, and Military
Temperatures
• 28-Pin 300 mil SOIC or 330 mil SOIC (RoHS-
Compliant)
STK22C48
2Kx8 AutoStore nvSRAM
DESCRIPTION
The Simtek STK22C48 is a 16Kb fast static RAM with
a nonvolatile Quantum Trap storage element included
with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use, and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the STORE
operation). On power-up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest-performance, most reliable non-volatile
memory available.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
VCCX VCAP
Quantum Trap
32 x 512
STATIC RAM
ARRAY
32 x 512
STORE
RECALL
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1 Document Control #ML0004 Rev 0.3
February 2007

1 page




STK22C48 pdf
SYMBOLS
NO.
#1 #2 Alt.
PARAMETER
14 tELWH
tELEH
tCW Chip Enable to End of Write
15 tDVWH
tDVEH
tDW Data Set-up to End of Write
16 tWHDX
tEHDX
tDH Data Hold after End of Write
17 tAVWH
tAVEH
tAW Address Set-up to End of Write
18 tAVWL
tAVEL
tAS Address Set-up to Start of Write
19 tWHAX
20 tWLQZ i, j
tEHAX
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
21 tWHQX
tOW Output Active after End of Write
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
ADDRESS
12
tAVAV
14
tELWH
E
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
DATA OUT
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledk, l
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
STK22C48
STK22C48-25 STK22C48-45
UNITS
MIN MAX MIN MAX
20 30
ns
10 15
ns
0 0 ns
20 30
ns
0 0 ns
0 0 ns
10 15 ns
5 5 ns
19
tWHAX
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
Document Control #ML0004 Rev 0.3
February 2007
5

5 Page





STK22C48 arduino
ORDERING INFORMATION
STK22C48 - N F 45 I TR
STK22C48
Packing Option
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
25 = 25ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
N = Plastic 28-pin 300 mil SOIC
S = Plastic 28-pin 330 mil SIOC
Document Control #ML0004 Rev 0.3
February 2007
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