PDF STK14C88-M Data sheet ( Hoja de datos )

Número de pieza	STK14C88-M
Descripción	32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM
Fabricantes	Simtek
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No Preview Available ! www.DataSheet4U.com STK14C88-M 32K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM MIL-STD-883 FEATURES • Nonvolatile Storage without Battery Problems • 35ns and 45ns Access Times • “Hands-off” Automatic STORE with External 68µF Capacitor on Power Down • STORE to EEPROM Initiated by Hardware, Software or AutoStore™ on Power Down • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 100,000 STORE Cycles to EEPROM • 10-Year Data Retention in EEPROM • Single 5V + 10% Operation • Not Sensitive to Power On/Off Ramp Rates • No Data Loss from Undershoot • 32-Pad LCC and 32-Pin 300 mil CDIP Packages DESCRIPTION The Simtek STK14C88-M is a fast static RAM with a nonvolatile, electrically erasable PROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) can take place auto- matically on power down. A 68µF or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power from “hot swapping”. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on restoration of power. Ini- tiation of STORE and RECALL cycles can also be software controlled by entering speciﬁc read sequences. A hardware STORE may be initiated with the HSB pin. BLOCK DIAGRAM A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 EEPROM ARRAY 512 x 512 STATIC RAM ARRAY 512 x 512 STORE RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 VCCX VCAP POWER CONTROL STORE/ RECALL CONTROL SOFTWARE DETECT PIN CONFIGURATIONS HSB VCAP A 14 A 12 A7 A6 A5 A4 A3 NC A2 A1 A0 DQ 0 DQ 1 DQ 2 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCCX 31 HSB 30 W 29 A13 A 4 5 3 2 1 32 31 30 29 A 28 A8 6 A6 13 28 A 27 A9 5 A7 8 27 A 26 A11 25 G 4 A8 3 9 32 26 A 11 NC 9 25 G 24 NC A 10 LCC 24 NC 23 A10 2 A 11 23 A 22 E 1 10 A 12 22 E 21 DQ 7 0 DQ 13 21 DQ 20 DQ 6 0 14 15 16 17 18 19 20 7 19 DQ 5 18 DQ 4 17 DQ 3 A0 - A13 G E W PIN NAMES A0 - A14 DQ0 -DQ7 E W G HSB VCCX VCAP VSS Address Inputs Data In/Out Chip Enable Write Enable Output Enable Hardware Store Busy (I/O) Power (+ 5V) Capacitor Ground April 1999 5-43 1 page STK14C88-M HARDWARE MODE SELECTION E W HSB A13 - A0 (hex) HXH X L HH X L LH X XXL X L HH 0E38 31C7 03E0 3C1F 303F 0FC0 L HH 0E38 31C7 03E0 3C1F 303F 0C63 MODE Not Selected Read SRAM Write SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output High Z Output Data Input Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z POWER Standby Active Active lCC2 Active lCC2 Active NOTES p m n, o, p n, o, p Note m: HSB store operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the store (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises. Note n: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. Note o: While there are 15 addresses on the STK14C88-M, only the lower 14 are used to control software modes. Note p: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. HARDWARE STORE CYCLE (VCC = 5.0V ± 10%)e SYMBOLS NO. Standard Alternate PARAMETER 22 tSTORE tHLHZ 23 tDELAY tHLQZ 24 tRECOVER tHHQX 25 tHLHX 26 tHLBL STORE Cycle Duration Time Allowed to Complete SRAM Cycle Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy Note q: E and G low and W high for output behavior. Note r: tRECOVER is only applicable after tSTORE is complete. STK14C88-M MIN MAX 10 1 700 20 300 UNITS NOTES ms i, q µs i, q ns q, r ns ns HARDWARE STORE CYCLE HSB (IN) 25 tHLHX 22 tSTORE 24 tRECOVER HSB (OUT) DQ (DATA OUT) 26 tHLBL HIGH IMPEDANCE 23 tDELAY DATA VALID HIGH IMPEDANCE DATA VALID April 1999 5-47 5 Page 100 80 60 40 TTL 20 CMOS 0 50 100 150 200 Cycle Time (ns) Figure 5: ICC (max) Reads STK14C88-M 100 80 60 TTL 40 CMOS 20 0 50 100 150 200 Cycle Time (ns) Figure 6: ICC (max) Writes April 1999 5-53 11 Page

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