PDF STK12C68-M Data sheet ( Hoja de datos )

Número de pieza	STK12C68-M
Descripción	CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM
Fabricantes	Simtek
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No Preview Available ! www.DataSheet4U.com STK12C68-M FEATURES STK12C68-M CMOS nvSRAM 8K x 8 AutoStore™ Nonvolatile Static RAM MIL-STD-883 / SMD # 5962-94599 DESCRIPTION • 40, 45 and 55ns Access Times • 15 mA ICC at 200ns Access Speed • Automatic STORE to EEPROM on Power Down • Hardware or Software initiated STORE to EEPROM • Automatic STORE Timing • 100,000 STORE cycles to EEPROM • 10 year data retention in EEPROM • Automatic RECALL on Power Up • Software initiated RECALL from EEPROM • Unlimited RECALL cycles from EEPROM • Single 5V±10% Operation • Available in multiple standard packages The Simtek STK12C68-M is a fast static RAM (40, 45 and 55ns), with a nonvolatile EEPROM element incor- porated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 µF capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. Software sequences may also be used to initiate both STORE and RECALL operations. A STORE can also be initiated via a single pin. The STK12C68-M is available in the following pack- ages: a 28-pin 300 mil ceramic DIP and 28-pad LCC. LOGIC BLOCK DIAGRAM A3 A4 A 5 A6 A7 A8 A9 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 EEPROM ARRAY 256 x 256 STATIC RAM ARRAY 256 x 256 STORE RECALL COLUMN I/O COLUMN DECODER A 0 A 1 A 2 A10 A11 A 0 A 12 STORE/ RECALL CONTROL 4-53 PIN CONFIGURATIONS HSB A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 32 28 27 4 1 26 5 25 6 24 7 23 8 TOP VIEW 22 9 21 10 20 11 19 12 18 13 14 15 16 17 HSB A8 A9 A11 G A10 E DQ7 DQ 6 VCAP A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ 0 DQ 1 DQ 2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VCCX 27 W 26 HSB 25 A 8 24 A 9 23 A 11 22 G 21 A 10 20 E 19 DQ 7 18 DQ 6 17 DQ 5 16 DQ 4 15 DQ 3 28 - LCC 28 - 300 C-DIP PIN NAMES A0 - A12 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G G Output Enable VCCX Power (+5V) VSS Ground E VCAP Capacitor W HSB Hardware Store/Busy 1 page NONVOLATILE MEMORY OPERATION STK12C68-M MODE SELECTION E W HSB A12 - A0(hex) MODE I/O POWER NOTES HXH X Not Selected Output High Z Standby L HH X Read SRAM Output Data Active l L LH X Write SRAM Input Data Active L HH 0000 Read SRAM Output Data Active k,l 1555 Read SRAM Output Data k,l 0AAA Read SRAM Output Data k,l 1FFF Read SRAM Output Data k,l 10F0 Read SRAM Output Data k,l 0F0F Nonvolatile STORE Output High Z k L HH 0000 Read SRAM Output Data Active k,l 1555 Read SRAM Output Data k,l 0AAA Read SRAM Output Data k,l 1FFF Read SRAM Output Data k,l 10F0 Read SRAM Output Data k,l 0F0E Nonvolatile RECALL Output High Z k XXL X STORE/Inhibit Output High Z ICC2/Standby m Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. Note l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G. Note m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the part will go into standby mode inhibiting all operation until HSB rises. HARDWARE STORE /RECALL SYMBOLS NO. PARAMETER MIN MAX UNITS NOTES 22 tRECALL RECALL Cycle Duration 23 tSTORE tHLHH STORE Cycle Duration 24 tDELAY tHLQZ HSB Low to Inhibit On 25 tRECOVER tHHQX HSB High to Inhibit Off 26 tASSERT tHLHX External STORE Pulse Width VSWITCH Low Voltage Trigger Level IHSB_OL HSB Output Low Current IHSB_OH HSB Output High Current 20 µs 10 ms 1 µs 300 ns 250 ns 4.0 4.5 V 3 mA 5 60 µA Note o VCC ≥ 4.5V Note e Note e HSB = VOL, Note e, n HSB = VIL, Note e, n Note e: Note n: Note o: These parameters guaranteed but not tested. HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-Ms to be ganged together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68-M HSB pins. A RECALL cycle is initiated automatically at power up when VCC exceeds VSWITCH. tRECALL is measured from the point at which VCC exceeds 4.5V. HARDWARE STORE /RECALL VSWITCH VCAP HSB W RECALL 24 tDELAY 22 tRECALL STORE SRAM Inhibit Power Up RECALL Brown Out RECALL 23 tSTORE Power Down STORE 4-57 26 tASSERT 24 tDELAY 25 tRECOVER 23 tSTORE HSB Initiated STORE 23 tSTORE Software STORE 5 Page

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