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PDF ST40RA Data sheet ( Hoja de datos )
| Número de pieza | ST40RA | |
| Descripción | 32-bit Embedded SuperH Device | |
| Fabricantes | STMicroelectronics | |
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ST40RA
32-bit Embedded SuperH Device
DATASHEET
JTAG
UDI
JTAG
Debug
SCIF
SCIF
Timer (TMU)
Real-time clock
Interrupt ctrl
Clock ctrl
PLLs
Integer & FP
execution units
Registers
MMU
I Cache
MMU
D Cache
Cbus Bridge/
SuperHyway I/F
SuperHyway
Mailbox
PIO
interface
5 channel
DMA
controller
EMI
PCI I/F 66MHz
ST40 Local Memory I/F
32 data
PCI Peripherals
64 data
SDRAM
24 data
2 channel
control
MPX
Coprocessor
32 data
Flash
Peripherals
Overview
The ST40RA is the first member of the ST40 family. Based
on the SH-4, SuperH CPU core from SuperH Inc, the
ST40RA is designed to work as a standalone device, or as
part of a two chip solution for application specific systems.
Example applications the ST40RA is designed for include
digital consumer, embedded communications, industrial
and automotive. The high connectivity of the ST40 through
its PCI bus and its dual memory uses makes it a versatile
device, ideal for data-intensive and high performance
applications.
System features
s 32-bit SuperH CPU
q 64-bit hardware FPU (1.16 GFLOPS)
q 128-bit vector unit for matrix manipulations
q 166 MHz, 300 MIPS (DMIPS 1.1)
q Up to 664 Mbytes/s CPU bandwidth
q Direct mapped, on-chip, ICache (8 Kbytes) and DCache
(16 Kbytes)
s High-performance 5-channel DMA engine,
supporting 1D or 2D block moves and linked lists
s SuperHyway internal interconnect
q High throughput, low latency, split transaction packet
router
s Memory protection and VM system support
q 64-entry unified TLB, 4-entry instruction TLB
q 4 Gbytes address space
s Standard ST40 peripherals
q 2 synchronous serial ports with FIFO (SCIF)
q Timers and a real-time clock
IO devices
q Mailbox register for interprocessor communication
q Additional PIO
Bus interfaces
s Local memory interface SDRAM & DDR SDRAM
q Up to 100 MHz (1.6 Gbytes/s peak throughput)
s PCI interface - 32-bit, 66/33 MHz, 3.3 V
s Enhanced memory interface (EMI)
q 32-bit bus, up to 83 MHz, for attaching peripherals
q High-speed, sync mode, burst flash ROM support
q SDRAM support
q MPX initiator and target interface
q Programmable MPX bus arbiter
13 August 2003
ADCS 7260755H
STMicroelectronics
1/94
1 page  
ST40RA
B.1
B.1.1
B.1.2
B.1.3
B.1.4
B.2
B.2.1
B.2.2
B.2.3
B.2.4
B.2.5
B.3
B.3.1
B.3.2
B.3.3
B.4
B.4.1
B.5
B.5.1
B.5.2
B.6
B.6.1
B.6.2
B.7
B.7.1
B.7.2
B.7.3
B.8
B.8.1
B.8.2
B.8.3
ST40 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
tas.b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Store queue power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UBC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
System standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Type 2 configuration accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Software visible changes between STB1HC7 and ST40RAH8D . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Error behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Master abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMI/EMPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
EMPI burst mode operation: ST40RA MPX target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SDRAM initialization during boot from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
MPX boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Mailbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Test and set functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Module power-down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Accesses to modules in power-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PIO default functionality following reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PCI/PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Memory bridge functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Pad drive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
GPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Linked list support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2-D transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Protocol signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5/94 STMicroelectronics
ADCS 7260755H
5 Page 
5 System configuration
ST40RA
ST’s own tools include:
q C/C++ compilers,
q debugger,
q proprietary OS.
Third parties include:
q Microsoft: WindowsCE,
q Sun: JavaOS for consumers,
q WindRiver: VxWorks, Tornado tools,
q Linux,
q Insignia JVM,
q ANT browser.
4.5.2 Software compatibility
SH-4 core software
The ST40RA SH-4 core is binary code compatible with the Hitachi SH775x family.
Standard peripheral driver
The ST40 standard SCIF, timer, real-time clock and PIO are compatible with the ST40 SOC range
of devices and the Hitachi SH775x family.
Bus interface driver
The PCI, LMI, and EMI interfaces are register compatible with the ST40 SOC range of devices.
The ST40RA contains an EMPI and MPX arbiter and MPX clock control unit which are additional to
the bus interface components of the ST40 SOC range of devices.
I/O device driver
The Mailbox is a module with no ST legacy software.
5 System configuration
The ST40RA system address map has been designed to maintain compatibility with existing ST40
family devices and other STMicroelectronics devices.
The SH-4 core and core peripherals maintain compatibility with the ST40 SOC range of devices and
Hitachi SH7750 wherever possible.
Devices listed in Table 2: ST40RA system address map on page 13, are documented in the ST40
System Architecture Manual as described in Chapter 2: ST40 documentation suite on page 6.
Coherency between the cache and external memory is assured by software. The ST40 CPU has
cache control instructions which enable software to do this. Details of these instructions are given in
the ST40 CPU Core Architecture Manual.
The ST40RA is run in little endian mode.
11/94 STMicroelectronics
ADCS 7260755H
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST40RA.PDF ] | |
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