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PDF XRD98L62 Data sheet ( Hoja de datos )
| Número de pieza | XRD98L62 | |
| Descripción | CCD Image Digitizers | |
| Fabricantes | Exar | |
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Preliminary
XRD98L62
CCD Image Digitizers with
CDS, PGA and 12-Bit A/D
FEATURES
• 12-bit Resolution ADC
• 30MHz Sampling Rate
• 10-bit Programmable Gain: 0dB to 36dB PGA
• Digitally Controlled Offset-Calibration with Pixel
Averager and Hot Pixel Clipper
• DNS Filter Removes Black Level Digital Noise
• Widest Black Level Calibration Range at
Maximum Gain
• 1ns/step Programmable Aperture Delay on SPIX,
SBLK and ADCLK
• Manual Control of Offset DAC via Serial Port for
use with High-speed Scanners
• Single 2.7V to 3.6V Power Supply
• Optimize Power with External Resistor to 180mW
• View Finder Mode, 6-bit Resolution, 25%
Less Power
• Low Power for Battery Operation
July 2000-4
• Two Serial Controlled 8-bit D/A Converters
• 0.5mA Stand-by Mode Current
• Three-state Digital Outputs
• 2,000V ESD Protection
• 48-pin TQFP Package
APPLICATIONS
• Mega pixel Digital Still Cameras
• Digital Camcorders
• 3 CCD Professional/Broadcast Camera
• Line Scan Cameras
• PC Video Cameras
• CCTV/Security Cameras
• Industrial/Medical Cameras
• 2D Bar Code Readers
• High Speed Scanners
• Digital Copiers
GENERAL DESCRIPTION
The XRD98L62 is a complete, low power CCD Image
Digitizer for digital motion and still cameras. The
product includes a high bandwidth differential Corre-
lated Double Sampler (CDS), 10-bit digitally Program-
mable Gain Amplifier (PGA), 12-bit Analog-to-Digital
Converter (ADC) and improved digitally controlled
black level auto-calibration circuitry with program-
mable pixel averager, hot pixel clipper, and a DNS
filter.
Two 8-bit serial controlled digital-to-analog converter
(DACs) are provided to control external analog signals
(Iris, Focus, Flash, etc.)
The Correlated Double Sampler (CDS) subtracts the
CCD output signal black level from the video level.
Common mode signal and power supply noise are
rejected by the differential CDS input stage.
ORDERING INFORMATION
The PGA is digitally controlled with 10-bit resolution on
a linear dB scale, resulting in a gain range of 0dB to
36dB with 0.047dB per LSB of the gain code.
The auto calibration circuit compensates for any inter-
nal offset of the XRD98L62 as well as black level offset
from the CCD.
The PGA and black level auto-calibration are con-
trolled through a simple 3-wire serial interface. The
timing circuitry is designed to enable users to select a
wide variety of available CCD and image sensors for
their applications. Readback of the serial data regis-
ters is available from the digital output bus.
The XRD98L62 has direct access to the ADC and PGA
inputs for digitizing other analog signals.
The XRD98L62 is packaged in 48-lead TQFP to reduce
space and weight, and is suitable for hand-held and
portable applications.
Part No.
Package Temperature Range
XRD98L62ACV 48-Pin TQFP
-15°C to 70°C
Operating
Power Supply
3.0V
Maximum
Sampling Rate
30 MSPS
Rev. P2.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
Preliminary
XRD98L62
DC ELECTRICAL CHARACTERISTICS – XRD98L62
Unless otherwise specified: OVDD = DVDD =AVDD = 3.0V, Pixel Rate = 30MSPS, TA = 25°C
Rext= 20KOhm
Symbol Parameter
Min. Typ. Max. Unit Conditions
CDS Performance
CDSVIN
VDARK
Vrst
Input Range
Maximum Dark Voltage Offset
Reset Pulse
800 mVPP Pixel (VBLK - VVIDEO), (See Figure 2).
250 mV At any gain. (See Figure 2).
500 mV
rCLAMP
Clamp On Resistance
PGA Parameters
120 Ω
AVMIN
AVMAX
PGA n
Minimum Gain
Maximum Gain
Resolution
0 dB Gain Code = 0
36 dB Gain Code > 768
10 bits Transfer function is linear steps in dB
PGA Step Gain Step Size
0.047
dB
ADC Parameters (Measured in ADC Test Mode)SDI = 0010 001 0011 1000
ADC n Resolution
12 bits
fs
DNL
Max Sample Rate
Differential Non-Linearity
30 MSPS
-1 +0.75 1 LSB
VID Full Scale Differential Input
+1.0
∆VREF
ADC Reference Voltage
1 V CapP - CapN = ∆VREF
Rev. P2.00
5
5 Page 
Preliminary
XRD98L62
Address bits
Data bits
Reg. Name A5 A4 A3 A2 A1 A0 D9 D8 D7 D6
D5 D4 D3 D2 D1 D0
Gain
Offset
Calibration
Wait A
Wait B
OB Lines
CDAC
FDAC
Control
Polarity
Clock
Delay A
Delay B
DAC0
DAC1
PGA[9] PGA[8] PGA[7] PGA[6]
000000
0
0
0
0
PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]
00 0 0 0 0
000001
OB[7]
1
OB[6]
0
OB[5] OB[4]
00
OB[3]
0
OB[2]
0
OB[1]
0
OB[0]
0
Avg[2]
000010
1
Avg[1]
0
Avg[0]
1
Mode
0
LFrame DNS[1] DNS[0] FastCal
01 1 1
Hold
0
ManCal
0
WL[11] WL[10]
000011
0
0
WL[9]
0
WL[8]
0
WL[7] WL[6]
00
WL[5]
0
WL[4]
0
WL[3]
0
WL[2]
0
000100
WL[1]
0
WL[0]
1
000101
OBL[7] OBL[6]
00
OBL[5] OBL[4] OBL[3] OBL[2] OBL[1] OBL[0]
00 0 0 1 0
000110
CDAC[8] CDAC[7] CDAC[6] CDAC[5] CDAC[4] CDAC[3] CDAC[2] CDAC[1] CDAC[0]
000
00 0 0 0 0
FDAC[9] FDAC[8] FDAC[7] FDAC[6] FDAC[5] FDAC[4] FDAC[3] FDAC[2] FDAC[1] FDAC[0]
000111
0
0
0
0
00 0 0 0 0
DIGtest ADCtest NoCDS LowPwr
001000
0
0
0
0
OE DAC1pd DAC0pd AFEpd ADCpd PwrDwn
11 1 0 0 0
001001
SBLKpol SPIXpol CALpol CLAMPpol FRpol ADCpol
00 0 0 0 0
CLKtest nullamp cmset
001010
0
0
0
fastclk CLAMPopt OneShot ClampCal SPIXopt RSTreject VSreject
0 00 0 0 0 0
001011
DelayA[8] DelayA[7] DelayA[6] DelayA[5] DelayA[4] DelayA[3] DelayA[2] DelayA[1] DelayA[0]
000
00 0 0 0 0
001100
DelayB[8] DelayB[7] DelayB[6] DelayB[5] DelayB[4] DelayB[3] DelayB[2] DelayB[1] DelayB[0]
000
00 0 0 0 0
001101
DAC0[7] DAC0[6] DAC0[5] DAC0[4] DAC0[3] DAC0[2] DAC0[1] DAC0[0]
00
00 0 0 0 0
001110
DAC1[7] DAC1[6] DAC1[5] DAC1[4] DAC1[3] DAC1[2] DAC1[1] DAC1[0]
00
00 0 0 0 0
ReadBack
Reset
RBenable RBreg[8] RBreg[7] RBreg[6]
111110
0
0
0
0
111111
RBreg[5] RBreg[4]
00
RBreg[3]
0
RBreg[2] RBreg[1]
00
RBreg[0]
0
Reset
0
Table 1. Serial Interface Register Address Map & default values
Gain
Default
D9
PGA[9]
0
D8
PGA[8]
0
D7
PGA[7]
0
D6
PGA[6]
0
D5
PGA[5]
0
D4
PGA[4]
0
D3
PGA[3]
0
D2
PGA[2]
0
D1
PGA[1]
0
D0
PGA[0]
0
Gain Register (Reg. 0, Address 000000)
The Gain register is used to set the gain of the Programmable Gain Amplifier (PGA).
Code 0000000000 is minimum gain (0 dB). Codes 1011111111 and greater are maximum gain (36 dB).
See the Programmable Gain Amplifier (PGA) section for more information.
Offset
Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OB[7] OB[6] OB[5] OB[4] OB[3] OB[2] OB[1] OB[0]
0010000000
Offset Register (Reg. 1, Address 000001)
The Offset register is used to set the target ADC output code for Optical Black pixels.
See the Black Level Offset Calibration section for more information.
Rev. P2.00
11
11 Page | ||
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| PDF Descargar | [ Datasheet XRD98L62.PDF ] | |
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