|
|
PDF XRT75R03 Data sheet ( Hoja de datos )
| Número de pieza | XRT75R03 | |
| Descripción | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XRT75R03 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
xrwww.DataSheet4U.com
XRT75R03
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
MARCH 2005
GENERAL DESCRIPTION
The XRT75R03 is a three-channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R3
Technology (Reconfigurable, Relayless Redundancy)
with Jitter Attenuator for E3/DS3/STS-1 applications.
It incorporates 3 independent Receivers,
Transmitters and Jitter Attenuators in a single 128 pin
LQFP package.
Each channel of the XRT75R03 can be
independently configured to operate in the data rate,
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz). Each transmitter can be turned off and tri-
stated for redundancy support or for conserving
power.
The XRT75R03’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75R03 incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications.
The XRT75R03 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75R03 supports local, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
FEATURES
RECEIVER:
TRANSMITTER:
REV. 1.0.7
• R3 Technology (Reconfigurable, Relayless
Redundancy)
• Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
• Tri-state Transmit output capability for redundancy
applications
• Each Transmitter can be independently turned on
or off
• Transmitters provide Voltage Output Drive
JITTER ATTENUATOR:
• On chip advanced crystal-less Jitter Attenuator for
each channel
• Jitter Attenuator can be selected in Receive or
Transmit paths
• Meets ETSI TBR 24 Jitter Transfer Requirements
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
• 16 or 32 bits selectable FIFO size
• Jitter Attenuator can be disabled
CONTROL AND DIAGNOSTICS:
• 5 wire Serial Microprocessor Interface for control
and configuration
• Supports optional internal Transmit driver
monitoring
• Hardware Mode for control and configuration
• Each channel supports Local, Remote and Digital
Loop-backs
• R3 Technology (Reconfigurable, Relayless
Redundancy)
• On chip Clock and Data Recovery circuit for high
input jitter tolerance
• Meets E3/DS3/STS-1 Jitter Tolerance Requirement
• Detects and Clears LOS as per G.775
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
• Provides low jitter output clock
• Single 3.3 V ± 5% power supply
• 5 V Tolerant digital inputs
• Available in 128 pin LQFP
• - 40°C to 85°C Industrial Temperature Range
APPLICATIONS
• E3/DS3 Access Equipment
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03
REV. 1.0.7
6.0 THE RECEIVER SECTION: ................................................................................................................. 43
6.1 AGC/EQUALIZER: .......................................................................................................................................... 43
6.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 44
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 44
FIGURE 19. INTERFERENCE MARGIN TEST SET UP FOR E3. ............................................................................................................ 45
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 45
6.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 45
6.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 46
6.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 46
6.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 46
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3
AND STS-1 APPLICATIONS)............................................................................................................................................. 46
DISABLING ALOS/DLOS DETECTION: .......................................................................................................... 46
6.4.2 E3 LOS CONDITION:.................................................................................................................................................. 46
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.......................................................................................... 47
FIGURE 21. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 47
6.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 48
7.0 JITTER: ................................................................................................................................................ 48
7.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 48
FIGURE 22. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 48
7.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 48
FIGURE 23. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 49
7.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 49
FIGURE 24. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 49
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................. 50
7.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 50
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................................................ 50
7.3 JITTER ATTENUATOR: ................................................................................................................................. 50
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 51
FIGURE 25. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 51
7.3.1 JITTER GENERATION: .............................................................................................................................................. 51
8.0 SERIAL HOST INTERFACE: ............................................................................................................... 51
TABLE 14: FUNCTIONS OF SHARED PINS ......................................................................................................................................... 52
TABLE 15: XRT75R03 REGISTER MAP - QUICK LOOK .................................................................................................................... 53
Legend: ..................................................................................................................................................................... 56
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75R03 3-CHANNEL DS3/E3/STS-1 LIU IC 56
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC56
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................ 58
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS ................................................................................................. 58
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................... 58
TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ............................................................... 58
TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20)....................................................... 61
TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21)....................................................... 62
TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E) ....................................................................... 63
TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F)..................................................................... 64
THE PER-CHANNEL REGISTERS ........................................................................................................... 64
TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................... 66
TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 .............................................. 66
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 .............................................. 68
TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03............................................................................. 70
TABLE 27: TRANSMIT CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X04 ..................................................................... 75
TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05 ....................................................................... 78
TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ...................................................................... 80
TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ..................................................... 83
9.0 DIAGNOSTIC FEATURES: ................................................................................................................. 84
9.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 84
FIGURE 26. PRBS MODE ............................................................................................................................................................. 84
9.2 LOOPBACKS: ................................................................................................................................................ 84
9.2.1 ANALOG LOOPBACK:............................................................................................................................................... 84
FIGURE 27. ANALOG LOOPBACK..................................................................................................................................................... 85
9.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 86
FIGURE 28. DIGITAL LOOPBACK...................................................................................................................................................... 86
II
5 Page 
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03
REV. 1.0.7
TRANSMIT LINE SIDE PINS
PIN #
SIGNAL NAME
TYPE
30 TTIP_0
11 TTIP_1
21 TTIP_2
O
28 TRing_0
13 TRing_1
19 TRing_2
O
DESCRIPTION
Transmit TTIP Output - Positive Polarity Signal - Channel 0:
Transmit TTIP Output - Positive Polarity Signal - Channel 1:
Transmit TTIP Output - Positive Polarity Signal - Channel 2:
These output pins along with the corresponding TRING_n output pins, function
as the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel, of
the XRT75R03.
Connect this signal and the corresponding TRING_n output signal to a 1:1
transformer.
Whenever the Transmit Section of the Channel generates and transmits a posi-
tive-polarity pulse onto the line, this output pin will be pulsed to a "higher-volt-
age" than its corresponding TRING_n output pins.
Conversely, whenever the Transmit Section of the Channel generates and
transmit a negative-polarity pulse onto the line, this output pin will be pulsed to a
"lower-voltage" than its corresponding TRING_n output pin.
NOTE: This output pin will be tri-stated whenever the corresponding TxON_n
input pin or bit-field is set to "0".
Transmit Ring Output - Negative Polarity Signal - Channel 0:
Transmit Ring Output - Negative Polarity Signal - Channel 1:
Transmit Ring Output - Negative Polarity Signal - Channel 2:
These output pins along with the corresponding TTIP_n output pins, function as
the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel,
within the XRT75R03.
Connect this signal and the corresponding TTIP_n output signal to a 1:1 trans-
former.
Whenever the Transmit Section of the Channel generates and transmits a posi-
tive-polarity pulse onto the line. This output pin will be pulsed to a "lower-volt-
age" than its corresponding TTIP_n output pins.
Conversely, whenever the Transmit Section of the Channel generates and
transmit a negative-polarity pulse onto the line. This output pin will be pulsed to
a "higher-voltage" than its corresponding TTIP_n output pin.
NOTE: This output pin will be tri-stated whenever the corresponding TxON_n
input pin or bit-field is set to "0".
8
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT75R03.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XRT75R03 | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | Exar Corporation |
| XRT75R03D | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | Exar Corporation |
| XRT75R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | Exar Corporation |
| XRT75R06D | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT | Exar Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |