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PDF XR19L222 Data sheet ( Hoja de datos )
| Número de pieza | XR19L222 | |
| Descripción | TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER | |
| Fabricantes | Exar Corporation | |
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XR19L222
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
MAY 2007
REV. 1.0.0
GENERAL DESCRIPTION
The XR19L222 (L222) is a highly integrated device that
combines a full-featured two channel Universal
Asynchronous Receiver and Transmitter (UART) and RS-
232 transceivers. The L222 is designed to operate with a
single 3.3V or 5V power supply. The L222 is fully compliant
with EIA/TIA-232-F Standards from a +3.3V to +5.5V power
supply. The device operates at 1 Mbps data rate with worst
case 3K ohms load. Both RS-232 driver outputs and
receiver inputs can operate in harsh electrical environments
of +/-15V without damage and can survive multiple +/-15kV
ESD on the RS-232 lines, while maintaining RS-232 output
levels.
The L222 operates in four different modes: Active, Partial
Sleep, Full Sleep and Power-Save. Each mode can be
invoked via hardware or software. Upon power-up, the
L222 is in the Active mode where the UART and RS-232
transceiver function normally. In the Partial Sleep mode, the
internal crystal oscillator of the UART or charge pump of the
RS-232 transceiver is turned off. In Full Sleep mode, both
the crystal oscillator and the charge pump are turned off.
While the UART is in the Sleep mode, the Power-Save
mode isolates the core logic from the control signals (chip
select, read/write strobes, address and data bus lines) to
minimize the power consumption. The RS-232 receivers
remain active in any of these four modes.
APPLICATIONS
• Battery-Powered Equipment
• Handheld and Mobile Devices
• Handheld Terminals
• Industrial Peripheral Interfaces
• Point-of-Sale (POS) Systems
FEATURES
• Meets true EIA/TIA-232-F Standards from +3.3V to +5.5V
operation
• Up to 1 Mbps data transmission rate
• 45us sleep mode exit (charge pump to full power)
• ESD protection for RS-232 I/O pins at
■ +/-15kV - Human Body Model
■ +/-15kV - 61000-4-2, Air-Gap Discharge
■ +/- 8kV - 61000-4-2, Contact Discharge
• Software compatible with industry standard 16550 UART
• Intel/Motorola bus select
• Complete modem interface
• Sleep and Power-save modes to conserve battery power
• Wake-up interrupt upon exiting low power modes
FIGURE 1. BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CSA# (CS#)
CSB#
INTA (IRQ#)
INTB
RESET (RESET#)
I/M#
RXBSEL
*5 V Tolerant
Inputs
Crystal
Osc/Buffer
BRG
64 Byte
TX & RX
FIFO
Modem
I/Os
Channel A
Channel B
UART
XR19L222
TXA
RXA
RTSA#
DTRA#
CTSA#
DSRA#
RIA#
CDA#
CDB#
RIB#
DSRB#
CTSB#
DTRB#
RTSB#
TXB
RXB
Charge Pump
5K
5K
5K
5K
Ch A Transceiver5K
Channel B
Transceiver
(See Figure 6)
RS-232 Transceiver
VREF+
VREF-
TXDA
RXDA
RTSA
DTRA
CTSA
DSRA
RIA
CDA
CDB
RIB
DSRB
CTSB
DTRB
RTSB
TXDB
TXB
RXDB
RXB
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.0
Pin Descriptions
XR19L222
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
NAME
64-QFN
PIN#
TYPE
DESCRIPTION
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
XTAL1
18
I Crystal or external clock input. This input is not 5V tolerant.
XTAL2 19 O Crystal or buffered clock output. This output may be use to drive a clock buffer which can
drive other device(s).
PwrSave 14
I Power-Save (active high). This feature isolates the L222’s data bus interface from the host
preventing other bus activities that cause higher power drain during sleep mode. See Sleep
Mode with Auto Wake-up and Power-Save Feature section for details.
ACP
25 I Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut
off if the L222 is already in partial sleep mode, i.e. the crystal oscillator is stopped. See
”Section 2.18, Sleep Modes and Power-Save Feature with Wake-Up Inter-
rupt” on page 20.
I/M# 30 I Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
RESET
(RESET#)
47
I When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period (see Table 16).
C2+ 46 - Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed
C2- 45
between these 2 pins.
C1+ 52 - Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor should be placed
C1- 51
between these 2 pins.
VREF+
53 Pwr +5.0V generated by the charge pump.
VREF-
27 Pwr -5.0V generated by the charge pump.
R_EN 24 I When the supply voltage is < 3.6V, connect R_EN to GND.
When the supply voltage is > 3.6V, connect R_EN to VCC.
C3A 55 I When the supply voltage is 3.3 V, C3A and C3B should be connected to VCC.
C3B 56
When the supply voltage is 5 V, C3A should be connected to C3B with a 1 uF capacitor to
GND.
RXBSEL
8
I When RXBSEL is HIGH, RXB is the input to the receiver of the UART.
When RXBSEL is LOW, RXDB is the input to the receiver of the UART.
FAST 21 I When FAST is HIGH, the maximum serial data rate is 1 Mbps.
When FAST is LOW, the maximum serial data rate is 250 Kbps.
VCC
48, 54 Pwr 3.3V to 5.5V power supply. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
GND 2, 17, 22, Pwr Power supply common, ground.
35
5
5 Page 
XR19L222
REV. 1.0.0
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
voltage at the pin should be 3.3V when an external clock is supplied. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS
XTAL1
C1
22-47pF
XTAL2
R2
500K - 1M
R1
0-120
(Optional)
Y1
1.8432 MHz
to
24 MHz
C2
22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. When VCC = 5V, the on-chip oscillator
can operate with a crystal whose frequency is not greater than 24 MHz. On the other hand, the L222 can
accept an external clock of up to 64 MHz at XTAL1 pin also. Although the L222 can accept an external clock of
up to 50MHz, the maximum data rate supported by the RS-232 drivers is 1Mbps. For further reading on the
oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com.
2.10 Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data
bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value
of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during
initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and
the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented
and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming
the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data
rate. Table 5 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate.
If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 5. At
8X sampling rate, these data rates would double. Also, when using 8X sampling mode, please note that the bit-
time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-
standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16X mode EMSR[7] = 1
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode EMSR[7] = 0
11
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| PDF Descargar | [ Datasheet XR19L222.PDF ] | |
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