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PDF XR16V2552 Data sheet ( Hoja de datos )
| Número de pieza | XR16V2552 | |
| Descripción | HIGH PERFORMANCE DUART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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PRELIMINARY
XR16V2552
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
JUNE 2006
REV. P1.0.0
GENERAL DESCRIPTION
The XR16V25521 (V2552) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 16 byte TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
ST16C2552 and XR16L2552. The V2552 register set
is compatible to the ST16C2552 and the XR16L2552.
It supports the Exar’s enhanced features of
selectable FIFO trigger level, automatic hardware
(RTS/CTS) and software (Xon/Xoff) flow control, and
a complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Independent programmable
baud rate generators are provided in each channel to
select data rates up to 16 Mbps at 3.3 Volt with 4X
sampling clock. The V2552 is available in 44-pin
PLCC and 32-pin QFN packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 2.25 to 3.6 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s XR16L2552 in the
44-PLCC package
• Two independent UART channels
■ Register set identical to 16V2550
■ Data rate of up to 16 Mbps at 3.3 V, and
12.5 Mbps at 2.5 V with 4X sampling rate
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 16 bytes
■ Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode
■ Full modem interface
• Alternate Function Register
• Device Identification and Revision
• Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
• 44-PLCC and 32-QFN packages
FIGURE 1. XR16V2552 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset
8-bit Data
Bus
Interface
* 5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
IR
ENDEC
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 3.6 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. P1.0.0
Pin Description
NAME
RTSB#
32-QFN
PIN #
13
CTSB#
17
DTRB#
DSRB#
-
-
CDB#
-
RIB#
-
MFB#
-
PRELIMINARY
XR16V2552
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
44-PLCC
PIN #
23
28
27
29
30
31
19
TYPE
DESCRIPTION
O UART channel B Request-to-Send (active low) or general purpose out-
put. This port must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1], and IER[6].
I UART channel B Clear-to-Send (active low) or general purpose input.
It can be used for auto CTS flow control, see EFR[7], and IER[7]. This
input should be connected to VCC when not used.
O UART channel B Data-Terminal-Ready (active low) or general purpose
output. If this pin is not used, leave it unconnected.
I UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
I UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
I UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
O Multi-Function Output Channel B. This output pin can function as the
OP2B#, BAUDOUTB#, or RXRDYB# pin. One of these output signal
functions can be selected by the user programmable bits 1-2 of the
Alternate Function Register (AFR). These signal functions are
described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW
when MCR bit-3 is set HIGH (see MCR bit-3). MCR bit-3 defaults to a
logic 0 condition after a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the Baud
rate clock output is available at this pin.
ANCILLARY SIGNALS
XTAL1
4
XTAL2
5
RESET
12
VCC
GND
NC
26
20
18, 19
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring block
data transfers. See Table 2 for more details.
11
13
21
44, 33
22, 12
-
I Crystal or external clock input.
O Crystal or buffered clock output.
I Reset (active high) - A longer than 40 ns HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter out-
put will be held HIGH, the receiver input will be ignored and outputs are
reset during reset period (see Table 15).
Pwr 2.25 to 3.6V power supply. All input pins are 5V tolerant.
Pwr Power supply common, ground.
- No Connect.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
REV. P1.0.0
FIGURE 5. BAUD RATE GENERATOR
To Other
Channel
PRELIMINARY
XR16V2552
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL, DLM and DLD
Registers
MCR Bit-7=0
(default)
Fractional Baud
Rate Generator
Logic
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
MCR Bit-7=1
TABLE 5: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
400
2400
4800
9600
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
DIVISOR FOR 16x
Clock
(Decimal)
3750
625
312.5
156.25
150
78.125
60
52.0833
39.0625
30
26.0417
20
15
13.0208
9.7656
7.5
6.6667
6.5104
6
5
3.75
3.2552
3
2
1.6276
1.5
DIVISOR
OBTAINABLE IN
V2552
3750
625
312 8/16
156 4/16
150
78 2/16
60
52 1/16
39 1/16
30
26 1/16
20
15
13
9 12/16
7 8/16
6 11/16
6 8/16
6
5
3 12/16
3 4/16
3
2
1 10/16
1 8/16
DLM PROGRAM
VALUE (HEX)
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DLL PROGRAM DLD PROGRAM DATA ERROR
VALUE (HEX) VALUE (HEX)
RATE (%)
A6 0 0
71 0 0
38 8 0
9C 4 0
96 0 0
4E 2 0
3C 0 0
34 1 0.04
27 1 0
1E 0 0
1A 1 0.08
14 0 0
F 00
D 0 0.16
9 C 0.16
7 80
6 B 0.31
6 8 0.16
6 00
5 00
3 C0
3 4 0.16
3 00
2 00
1 A 0.16
1 80
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XR16V2552.PDF ] | |
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