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PDF XR16L2550 Data sheet ( Hoja de datos )
| Número de pieza | XR16L2550 | |
| Descripción | LOW VOLTAGE DUART | |
| Fabricantes | Exar Corporation | |
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XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
SEPTEMBER 2010
REV. 1.1.3
GENERAL DESCRIPTION
The XR16L25501 (L2550) is a dual universal
asynchronous receiver and transmitter (UART). The
XR16L2550 is an improved version of the
ST16C2550 UART with lower operating voltages and
5 volt tolerant inputs. The L2550 provides enhanced
UART functions with 16 byte FIFOs, a modem control
interface and data rates up to 4 Mbps. Onboard
status registers provide the user with error indications
and operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates up to 3.125
Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
L2550 is available in a 44-pin PLCC, 48-pin TQFP
and 32-pin QFN packages. The L2550 is fabricated in
an advanced CMOS process.
NOTE: 1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
• Portable Appliances
• Medical Monitors
• Base Stations
• Micro Servers
• Telecommunication Network Routers
• Industrial Automation Controls
FIGURE 1. XR16L2550 BLOCK DIAGRAM
FEATURES
• 2.25 to 5.5 Volt operation
• 5 Volt tolerant inputs
• Pin-to-pin compatible to Exar’s ST16C2450,
ST16C2550 and XR16L2750 in 44-PLCC and 48-
TQFP packages
• Pin-to-pin compatible to XR16C2850 in 44-PLCC
• Pin alike XR16L2551, XR16L2751 and
XR16C2850 in 48-TQFP package
• Two independent UART channels
■ Up to 3.125Mbps with external clock of 50 MHz
■ Register Set compatible to 16C550
■ 16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
■ 16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
■ 4 selectable Receive FIFO interrupt trigger
levels
■ Automatic RTS/CTS hardware flow control
■ Automatic Xon/Xoff software flow control
■ Wireless infrared encoder/decoder
■ Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
■ Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
• Tiny 32-QFN, no lead package (5x5x0.9mm)
• 44-PLCC and 48-TQFP packages also available
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
Reset
8-bit Data
Bus
Interface
* 5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 5.5 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.1.3
Pin Description
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
NAME
32-QFN 44-PLCC 48-TQFP
PIN #
PIN #
PIN #
TYPE
DESCRIPTION
RTSB#
15
27
22 O UART channel B Request-to-Send (active low) or general pur-
pose output. This output must be asserted prior to using auto
RTS flow control, see EFR[6], MCR[1] and IER[6]. If it is not
used, leave it unconnected.
CTSB#
16
28
23
I UART channel B Clear-to-Send (active low) or general purpose
input. It can be used for auto CTS flow control, see EFR[7] and
IER[7]. This input should be connected to VCC when not used.
DTRB#
-
38 35 O UART channel B Data-Terminal-Ready (active low) or general
purpose output. If it is not used, leave it unconnected.
DSRB#
-
25 20 I UART channel B Data-Set-Ready (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
CDB#
-
21 16 I UART channel B Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
RIB# - 26 21 I UART channel B Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used.
This input has no effect on the UART.
OP2B#
-
15
9 O Output Port 2 Channel B - The output state is defined by the user
and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to
a logic 1. INTB is set to the three state mode and OP2B# to a
logic 1 when MCR[3] is set to a logic 0. This output should not be
used as a general output else it will disturb the INTB output func-
tionality. If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
10
18
13
I Crystal or external clock input.
XTAL2
11
19
14 O Crystal or buffered clock output.
RESET
24
39
36
I Reset (active high) - A longer than 40 ns logic 1 pulse on this pin
will reset the internal registers and all outputs. The UART trans-
mitter output will be held at logic 1, the receiver input will be
ignored and outputs are reset during reset period.
VCC 26 44 42 Pwr 2.25V to 5.5V power supply. All inputs are 5V tolerant.
GND
GND
13
Center
Pad
22
N/A
17 Pwr Power supply common, ground.
N/A Pwr The center pad on the backside of the 32-QFN package is metal-
lic and should be connected to GND on the PCB. The thermal
pad size on the PCB should be the approximate size of this cen-
ter pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the
PCB thermal pad.
N.C. 9, 17
- 12, 24,
25, 37
No Connection. These pins are open, but typically, should be con-
nected to GND for good design practice.
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
5
5 Page 
XR16L2550
REV. 1.1.3
LOW VOLTAGE DUART WITH 16-BYTE FIFO
The L2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock
by any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
400
DIVISOR FOR 16x
Clock (Decimal)
2304
DIVISOR FOR 16x
Clock (HEX)
900
DLM PROGRAM
VALUE (HEX)
09
DLL PROGRAM
VALUE (HEX)
00
DATA RATE
ERROR (%)
0
2400
384 180
01
80 0
4800 192 C0 00 C0 0
9600
96
60
00
60 0
19.2k
48
30
00
30 0
38.4k
24
18
00
18 0
76.8k
12
0C
00
0C 0
153.6k
6
06 00
06 0
230.4k
4
04 00
04 0
460.8k
2
02 00
02 0
921.6k
1
01 00
01 0
2.11 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.11.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.11.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
11
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