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PDF LPC660 Data sheet ( Hoja de datos )

Número de pieza LPC660
Descripción Low Power CMOS Quad Operational Amplifier
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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March 1998
LPC660
Low Power CMOS Quad Operational Amplifier
General Description
The LPC660 CMOS Quad operational amplifier is ideal for
operation from a single supply. It features a wide range of
operating voltages from +5V to +15V and features rail-to-rail
output swing in addition to an input common-mode range
that includes ground. Performance limitations that have
plagued CMOS amplifiers in the past are not a problem with
this design. Input VOS, drift, and broadband noise as well as
voltage gain (into 100 kand 5 k) are all equal to or better
than widely accepted bipolar equivalents, while the power
supply requirement is typically less than 1 mW.
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
See the LPC662 datasheet for a Dual CMOS operational
amplifier and LPC661 datasheet for a single CMOS opera-
tional amplifier with these same features.
Applications
n High-impedance buffer
n Precision current-to-voltage converter
n Long-term integrator
n High-impedance preamplifier
n Active filter
n Sample-and-Hold circuit
n Peak detector
Features
n Rail-to-rail output swing
n Micropower operation:
n Specified for 100 kand 5 kloads
n High voltage gain:
n Low input offset voltage:
n Low offset voltage drift:
n Ultra low input bias current:
n Input common-mode includes V
n Operation range from +5V to +15V
n Low distortion:
n Slew rate:
n Full military temp. range available
(1 mW)
120 dB
3 mV
1.3 µV/˚C
2 fA
0.01% at 1 kHz
0.11 V/µs
Connection Diagram
14-Pin DIP/SO
Top View
DS010547-1
© 1999 National Semiconductor Corporation DS010547
www.national.com

1 page




LPC660 pdf
AC Electrical Characteristics
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Parameter
Conditions
Typ LPC660AM LPC660AI LPC660I Units
LPC660AMJ/883
Limit
Limit
Limit
(Notes 4, 8)
(Note 4) (Note 4)
Slew Rate
(Note 6)
0.11
0.07
0.07
0.05
V/µs
0.04
0.05
0.03
min
Gain-Bandwidth Product
0.35
MHz
Phase Margin
50 Deg
Gain Margin
17 dB
Amp-to-Amp Isolation
(Note 7)
130
dB
Input Referred Voltage Noise F = 1 kHz
42
Input Referred Current Noise F = 1 kHz
0.0002
Total Harmonic Distortion
F = 1 kHz, AV = −10
RL = 100 k, VO = 8 VPP
0.01
%
Note 1: Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts
can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ±30 mA over long term may adversely affect reliability.
Note 2: The maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD =
(TJ(max)–TA)θJA.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 4: Limits are guaranteed by testing or correlation.
Note 5: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 2.5V VO 7.5V.
Note 6: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 7: Input referred. V+ = 15V and RL = 100 kconnected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP.
Note 8: A military RETS electrical test specification is available on request. At the time of printing, the LPC660AMJ/883 RETS specification complied fully with the
boldface limits in this column. The LPC660AMJ/883 may also be procured to a Standard Military Drawing specification.
Note 9: For operating at elevated temperatures, the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA.
Note 10: All numbers apply for packages soldered directly into a PC board.
Note 11: Do not connect output to V+when V+ is greater than 13V or reliability may be adversely affected.
Typical Performance Characteristics VS = ± 7.5V, TA = 25˚C unless otherwise specified
Supply Current
vs Supply Voltage
Input Bias Current
vs Temperature
Common-Mode Voltage
Range vs Temperature
DS010547-27
DS010547-28
5
DS010547-29
www.national.com

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LPC660 arduino
Application Hints (Continued)
DS010547-24
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 6. Air Wiring
BIAS CURRENT TESTING
The test method of Figure 7 is appropriate for bench-testing
bias current with reasonable accuracy. To understand its op-
eration, first close switch S2 momentarily. When S2 is
opened, then
DS010547-25
FIGURE 7. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver
mica, NPO ceramic, or air-dielectric. When determining the
magnitude of I, the leakage of the capacitor and socket
must be taken into account. Switch S2 should be left shorted
most of the time, or else the dielectric absorption of the ca-
pacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2
shorted)
where Cx is the stray capacitance at the + input.
Typical Single-Supply Applications (V+ = 5.0 VDC)
Photodiode Current-to-Voltage Converter
Micropower Current Source
DS010547-17
Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2
or 3, leading to improved response and lower noise. However, this bias on
the photodiode will cause photodiode leakage (also known as its dark
current).
DS010547-18
Note: (Upper limit of output range dictated by input common-mode range;
lower limit dictated by minimum current requirement of LM385.)
11 www.national.com

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