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PDF MSM54V32126A Data sheet ( Hoja de datos )
| Número de pieza | MSM54V32126A | |
| Descripción | DYNAMIC RAM | |
| Fabricantes | OKI electronic | |
| Logotipo |  |
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E2L0053-17-Y1
www.DataSheet4U.com
¡¡SemicondSucetormiconductor
This verMsiSonM: 5J4aVn3. 21919286A
MSM54V32126A
131,072-Word ¥ 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM54V32126A is a Graphics DRAM organized in a 131,072-word ¥ 32-bit configuration. The
technology used to fabricate the MSM54V32126A is OKI's CMOS silicon gate process technology.
The device operates with a single 3.3 V power supply.
FEATURES
• 131,072-word ¥ 32-bit organization
• Single 3.3 V power supply, ±0.3 V tolerance
• Refresh: 512 cycles/8 ms
• Fast Page Mode with Extended Data Out (EDO)
• Byte write, Byte read
• RAS only refresh
• CAS before RAS refresh
• CAS before RAS self-refresh
• Hidden refresh
• Package options:
64-pin 525 mil plastic SSOP
(SSOP64-P-525-0.80-K) (Product : MSM54V32126A-xxGS-K)
70/64-pin 400 mil plastic TSOP (Type II)(TSOPII70/64-P-400-0.65-K)(Product : MSM54V32126A-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM54V32126A-45
MSM54V32126A-50
MSM54V32126A-60
Access Time (Max.)
tRAC tAA tCAC tOEA
45 ns 23 ns 13 ns 13 ns
50 ns 25 ns 15 ns 15 ns
60 ns 30 ns 18 ns 18 ns
Cycle Time
(Min.)
90 ns
100 ns
120 ns
Power Dissipation
Operating (Max.) Standby (Max.)
540 mW
504 mW
3.1 mW
486 mW
1/26
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MSM54V32126A
DC Characteristics
(VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C)
Parameter
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
Condition
MSM54V32126A MSM54V32126A MSM54V32126A
-45 -50 -60 Unit Note
VOH IOH = –0.1 mA
VOL IOL = 0.1 mA
Min. Max. Min. Max. Min. Max.
2.0 VCC 2.0 VCC 2.0 VCC
0 0.8 0 0.8 0 0.8
V
V
0 V < VIN < VCC;
ILI All other pins not –10 10 –10 10 –10 10 mA
under test = 0 V
Output Leakage Current
ILO
0 V < VOUT < 3.6 V
Output Disable
–10
10
–10
10
–10
10
mA
Average Power
Supply Current
(Operating)
RAS, CAS cycling,
ICC1 tRC = Min.
— 140 — 130 — 110 mA 1, 2, 3
Power Supply
Current (Standby)
Average Power
Supply Current
(RAS Only Refresh)
ICC2
RAS ≥ VCC – 0.2 V,
CAS ≥ VCC – 0.2 V
—
850
—
850
—
850 mA
RAS = cycling,
ICC3 CAS = VIH,
tRC = Min.
— 140 — 130 — 110 mA 1, 2, 3
Average Power
Supply Current
(Fast Page Mode)
RAS = VIL,
ICC4 CAS cycling,
tHPC = Min.
— 150 — 140 — 135 mA 1, 2, 4
Average Power
Supply Current
(CAS before RAS Refresh)
ICC5
RAS = cycling,
CAS before RAS
— 140 — 130 — 110 mA 1, 2, 4
Average Power
Supply Current
(CAS before RAS
Self-Refresh)
ICCS
RAS = VIL,
CAS = VIL
— 950 — 950 — 950 mA 1, 2
Notes:
1. Specified values are obtained with minimum cycle time.
2. ICC is dependent on output loading. Specified values are obtained with the output
open.
3. Address can be changed once or less while RAS = VIL.
4. Address can be changed once or less while CAS = VIH.
5/26
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¡ Semiconductor
MSM54V32126A
Read Cycle (Outputs Controlled by CAS)
RAS
CAS1
|
,,,CAS4
tRC
tRAS
tCRP
tRCD
tRAD
tASR tRAH tASC
tCSH
tRSH
tCAS
tCAH tRAL
tRP
tCRP
tRCL
Address
Row Column
tAR tRCH
tRCS
tRRH
WE
OE
,DQ0-DQ31
Open
tRAC
tROH
tOEA
tCAC
tAA
tOEZ
Valid Data-out
tCEZ
"H" or "L"
11/26
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MSM54V32126A.PDF ] | |
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