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PDF PC33926 Data sheet ( Hoja de datos )
| Número de pieza | PC33926 | |
| Descripción | Throttle Control H-Bridge | |
| Fabricantes | Freescale Semiconductor | |
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Document Number: MC33926
Rev. 4.0, 12/2006
5.0 A Throttle Control H-Bridge
The 33926 is a monolithic H-Bridge Power IC designed primarily
for automotive electronic throttle control, but is applicable to any low-
voltage DC servo motor control application within the current and
voltage limits stated in this specification.
The 33926 is able to control inductive loads with currents up to
5.0 A peak. RMS current capability is subject to the degree of
heatsinking provided to the device package. Internal peak-current
limiting (regulation) is activated at load currents above 6.5 A ± 1.5 A.
Output loads can be pulse width modulated (PWM-ed) at frequencies
up to 20 kHz. A load current feedback feature provides a proportional
(0.24% of the load current) current output suitable for monitoring by a
microcontroller’s A/D input. A Status Flag output reports
undervoltage, overcurrent, and overtemperature fault conditions.
33926
AUTOMOTIVE THROTTLE H-BRIDGE
ACTUATOR/ MOTOR EXCITER
Two independent inputs provide polarity control of two half-bridge
totem-pole outputs. Two independent disable inputs are provided to
force the H-Bridge outputs to tri-state (high impedance off-state). An
input invert input changes the IN1 and IN2 inputs to LOW = true logic.
Features
BoStCtoAmLE V2:i1ew
PNB SUFFIX
98ARL10579D
32-PIN PQFN
• 8.0 V to 28 V Continuous Operation (Transient Operation from
5.0 V to 36 V)
• 225 mΩ maximum RDS(ON) @ 150°C (each H-Bridge MOSFET)
• 3.0 V and 5.0 V TTL / CMOS Logic Compatible Inputs
• Overcurrent Limiting (Regulation) via Internal Constant-Off-
Time PWM
• Output Short Circuit Protection (Short to VPWR or Ground)
ORDERING INFORMATION
Device
PC33926PNB/R2
Temperature
Range (TA)
- 40°C to 125°C
Package
32 PQFN
• Temperature-Dependant Current-Limit Threshold Reduction
• All Inputs have an Internal Source/Sink to Define the Default (Floating Input) States
• Sleep Mode with Current Draw < 50 µA (with Inputs Floating or Set to Match Default Logic States)
VDD
VPWR
MCU
33926
SF VPWR
FB CCP
IN1 OUT1
IN2
INV
SLEW
D1
OUT2
D2 PGND
EN AGND
MOTOR
Figure 1. 33926 Simplified Application Diagram
*This document contains certain information on a product under development. Free-
scale reserves the right to change or discontinue this product without notice
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device. These parameters are not production tested.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
Normal Operation (Steady-State)
Transient Overvoltage (1)
Logic Input Voltage (2)
SF Output (3)
Continuous Output Current (4)
ESD Voltage (5)
Human Body Model
Machine Model
Charge Device Model
Corner Pins (1,9,17,25)
All Other Pins
VPWR(SS)
VPWR(t)
VIN
V SF
IOUT(CONT)
VESD1
VESD2
-0.3 to 28
-0.3 to 40
-0.3 to 7.0
-0.3 to 7.0
5.0
± 2000
± 200
±750
±500
V
V
V
A
V
THERMAL RATINGS
Storage Temperature
Operating Temperature (6)
TSTG
- 65 to 150
°C
°C
Ambient
Junction
Peak Package Reflow Temperature During Reflow (7), (8)
TA
TJ
TPPRT
-40 to 125
-40 to 150
Note 8
°C
Approximate Junction-to-Board Thermal Resistance (9)
RθJB
< 1.0
°C/W
Notes
1. Device will survive repetitive transient overvoltage conditions for durations not to exceed 500 ms @ duty cycle not to exceed 10%.
External protection is required to prevent device damage in case of a reverse battery condition.
2. Exceeding the maximum input voltage on IN1, IN2, EN, INV, SLEW, D1, or D2 may cause a malfunction or permanent damage to the
device.
3. Exceeding the pullup resistor voltage on the open drain SF pin may cause permanent damage to the device.
4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature ≤150°C.
5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
non-repetitive excursions of junction temperature above 150°C can be tolerated provided the duration does not exceed 30 seconds
maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.)
7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
9. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum
die temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJA must be
<5.0°C/W for maximum current at 70°C ambient. Module thermal design must be planned accordingly.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33926
5
5 Page 
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
Numerous protection and operational features (speed,
torque, direction, dynamic breaking, PWM control, and
closed-loop control) make the 33926 a very attractive, cost-
effective solution for controlling a broad range of small DC
motors. The 33926 outputs are capable of supporting peak
DC load currents of up to 5.0 A from a 28 VPWR source. An
internal charge pump and gate drive circuitry are provided
that can support external PWM frequencies up to 20 kHz.
The 33926 has an analog feedback (current mirror) output
pin (the FB pin) that provides a constant-current source
ratioed to the active high-side MOSFETs’ current. This can be
used to provide “real time” monitoring of output current to
facilitate closed-loop operation for motor speed/torque
control, or for the detection of open load conditions.
Two independent inputs, IN1 and IN2, provide control of
the two totem-pole half-bridge outputs. An input invert, INV,
changes IN1 and IN2 to LOW = true logic. Two different
output slew rates are selectable via the SLEW input. Two
independent disable inputs, D1 and D2, provide the means to
force the H-Bridge outputs to a high impedance state (all H-
Bridge switches OFF). An EN pin controls an enable function
that allows the IC to be placed in a power-conserving Sleep
mode.
The 33926 has Output Current Limiting (via Constant
OFF-Time PWM Current Regulation), Output Short-Circuit
Detection with Latch-OFF, and Overtemperature Detection
with Latch-OFF. Once the device is latched-OFF due to a
fault condition, either of the Disable inputs (D1 or D2), VPWR,
or EN must be “toggled” to clear the status flag.
Current limiting (Load Current Regulation) is
accomplished by a constant-OFF time PWM method using
current limit threshold triggering. The current limiting scheme
is unique in that it incorporates a junction temperature-
dependent current limit threshold. This means that the
current limit threshold is “reduced to around 4.2 A” as the
junction temperature increases above 160°C. When the
temperature is above 175°C, overtemperature shutdown
(latch-OFF) will occur. This combination of features allows
the device to continue operating for short periods of time (<30
seconds) with unexpected loads, while still retaining
adequate protection for both the device and the load.
FUNCTIONAL PIN DESCRIPTION
POWER GROUND AND ANALOG GROUND
(PGND AND AGND)
The power and analog ground pins should be connected
together with a very low impedance connection.
POSITIVE POWER SUPPLY (VPWR)
VPWR pins are the power supply inputs to the device. All
VPWR pins must be connected together on the printed circuit
board with as short as possible traces, offering as low
impedance as possible between pins.
STATUS FLAG (SF)
This pin is the device fault status output. This output is an
active LOW open drain structure requiring a pullup resistor to
VDD. The maximum VDD is <7.0 V. Refer to Table 5, Truth
Table, page 14 for the SF Output status definition.
INPUT INVERT (INV)
The Input Invert Control pin sets IN1 and IN2 to
LOW = TRUE. This is a Schmitt trigger input with ~80 µA sink;
the default condition is non-inverted. If IN1 and IN2 are set so
that the current is being commanded to flow through the load
attached between OUT1 and OUT2, changing the logic level
at INV will have the effect of reversing the direction of current
commanded. Thus, the INV input may be used as a “forward/
reverse” command input. If both IN1 and IN2 are the same
logic level, then changing the logic level at INV will have the
effect of changing the bridge’s output from freewheeling high
to freewheeling low or vice versa.
SLEW RATE (SLEW)
The SLEW pin is the logic input that selects fast or slow
slew rate. Schmitt trigger input with ~80 µA sink so the default
condition is SLOW. When SLEW is set to SLOW, PWM-ing
should be limited to frequencies less than 11 kHz in order to
allow the internal high-side driver circuitry time to fully
enhance the high-side MOSFETs.
INPUT 1,2 AND DISABLE INPUT 1,2
(IN1, IN2, AND D1, D2)
These pins are input control pins used to control the
outputs. These pins are 3.0 V/5.0 V CMOS-compatible
inputs with hysteresis. IN1 and IN2 independently control
OUT1 and OUT2, respectively. D1 and D2 are
complementary inputs used to tri-state disable the H-Bridge
outputs.
When either D1 or D2 is SET (D1 = logic HIGH or
D2 = logic LOW) in the disable state, outputs OUT1 and
OUT2 are both tri-state disabled; however, the rest of the
device circuitry is fully operational and the supply
IPWR(STANDBY) current is reduced to a few mA. Refer to Table
3, Static Electrical Characteristics, page 6.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33926
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PC33926.PDF ] | |
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