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PDF MC68EC030 Data sheet ( Hoja de datos )
| Número de pieza | MC68EC030 | |
| Descripción | Second-Generation 32-Bit Enhanced Embedded Controller | |
| Fabricantes | Motorola Semiconductors | |
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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Order this document
by MC68EC030/D
MC68EC030
Technical Summary
Second-Generation 32-Bit Enhanced Embedded
Controller
The MC68EC030 is a 32-bit embedded controller that streamlines the functionality of an MC68030 for
the requirements of embedded control applications. The MC68EC030 is optimized to maintain
performance while using cost-effective memory subsystems. The rich instruction set and addressing
mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear
migration path for M68000 systems. The main features of the MC68EC030 are as follows:
• Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 Microprocessors
• Burst-Mode Bus Interface for Efficient DRAM Access
• On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)
• Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-Bit Devices
• 25- and 40-MHz Operating Frequency (up to 9.2 MIPS)
• Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications
Additional features of the MC68EC030 include:
• Complete 32-Bit Nonmultiplexed Address and Data Buses
• Sixteen 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and Eight Special-Purpose Control Registers
• Two Access Control Registers Allow Blocks To Be Defined for Cacheability Protection
• Pipelined Architecture with Increased Parallelism Allows:
– Internal Caches Accesses in Parallel with Bus Transfers
– Overlapped Instruction Execution
• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycle (two clocks minimum), and Burst Data Transfers (one clock)
• Complete Support for Coprocessors with the M68000 Coprocessor Interface
• Internal Status Indication for Hardware Emulation Support
• 4-Gbyte Direct Addressing Range
• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High-Density
NMOS) Gates To Be Combined for Maximum Speed, Low Power, and Small Die Size
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
©MOTOROLA INC., 1991
µ MOTOROLAFor More Information On This Product,
Rev. 1
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Freescale Semiconductor, Inc.
The ACU contains two access control registers that are used to define memory segments ranging in size
from 16 Mbytes to 2 Gbytes each. Each segment is definable in terms of address, read/write access, and
function code. Each segment can be marked as cacheable or non cacheable to control cache accesses
to that memory space.
PROGRAMMING MODEL
As shown in the programming models (see Figures 3 and 4), the MC68EC030 has 16 32-bit general-
purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, a 16-bit status register,
a 32-bit vector base register, two 3-bit alternate function code registers, two 32-bit cache handling
(address and control) registers, and two 32-bit transparent translation registers. Registers D0–D7 are
used as data registers for bit and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and
quad-word (64 bit) operations. Registers A0–A6 and the user, interrupt, and master stack pointers are
address registers that may be used as software stack pointers or base address registers. In addition, the
address registers may be used for word and long-word operations. All 16 general-purpose registers (D0–
D7, A0–A7) can be used as index registers.
31
16 15
87
0
D0
D1
D2
D3 DATA
D4 REGISTERS
D5
D6
D7
31 16 15
0
A0
A1
A2
A3
A4
A5
A6
ADDRESS
REGISTERS
31 16 15
31
0
A7
(USP)
0
PC
USER STACK
POINTER
PROGRAM
COUNTER
15
0
87
0
CCR
CONDITION CODE
REGISTER
Figure 3. User Programming Model
MOTOROLA
FMorCM68oEreC0In30forTmEaCtHioNnICOAnLThDisATPAroduct,
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cpBCC
cpDBcc
cpGEN
Coprocessor Instructions
Branch Conditionally
Test Coprocessor Condition,
Decrement and Branch
Coprocessor General Instruction
cpRESTORE
cpSAVE
cpScc
cpTRAPcc
Restore Internal State of Coprocessor
Save Internal State of Coprocessor
Set Conditionally
Trap Conditionally
Included in the MC68EC030 set are the bit field operations, binary-coded decimal support, bounds
checking, additional trap conditions, and additional multiprocessing support (CAS and CAS2 instructions)
offered by the MC68020, MC68030, and MC68040. In addition, object code written for the MC68EC030
can be used on the MC68040 for even more performance. The memory management unit (MMU)
instructions of the MC68030, and MC68040 are not supported by the MC68EC030.
INSTRUCTION AND DATA CACHES
Studies have shown that typical programs spend most of their execution time in a few main routines or
tight loops. This phenomenon, known as locality of reference, has an impact on program performance.
The MC68010 takes limited advantage of this phenomenon with the loop mode of operation that can be
used with the DBcc instruction. The MC68EC030 takes further advantage of cache technology to
provide the system with two on-chip caches, one for instructions and one for data.
MC68EC030 CACHE GOALS
Similar to the MC68020 and MC68030, there were two primary design goals for the MC68EC030
embedded controller caches. The first design goal was to reduce the external bus activity of the CPU
even more than was accomplished with the MC68020. The second design goal was to increase effective
CPU throughput as larger memory sizes or slower memories increased average access time. By placing a
high-speed cache between the controller and the rest of the memory system, the effective memory
access time becomes:
tacc =Rh*tcache + (1-Rh)*text
where tacc is the effective system access time, tcache is the cache access time, text is the access time of
the rest of the system, and Rh is the hit ratio or the percentage of time that the data is found in the cache.
Thus, for a given system design, the two MC68EC030 on-chip caches provide an even more substantial
CPU performance increase over that obtainable with the MC68020 instruction cache. Alternately, slower
and less expensive memories can be used for the same controller performance.
The throughput increase in the MC68EC030 is gained in three ways. First, the MC68EC030 caches are
accessed in less time than is required for external accesses, providing improvement in the access time for
items residing in the cache. Second, the burst filling of the caches allows instruction and data words to be
found in the on-chip caches the first time they are accessed by the micromachine, minimizing the time
required to bring those items into the cache. Utilizing burst fill capabilities lowers the average access time
for items found in the caches even further. Third, the autonomous nature of the caches allows instruction
stream fetches, data fetches, and external bus activity to occur simultaneously with instruction execution.
The parallelism designed into the MC68EC030 also allows multiple instructions to execute concurrently
so that several internal instructions (those that do not require any external accesses) can execute while
the controller is performing an external access for a previous instruction.
INSTRUCTION CACHE
MOTOROLA
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