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PDF LP62S1024BX-55LLTF Data sheet ( Hoja de datos )
| Número de pieza | LP62S1024BX-55LLTF | |
| Descripción | 128K X 8 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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LP62S1024B-T Series
Preliminary
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Add 32L Pb-Free TSSOP package type
Issue Date
February 19, 2002
October 2, 2002
Remark
Preliminary
PRELIMINARY (October, 2002, Version 0.1)
AMIC Technology, Corp.
1 page  
LP62S1024B-T Series
Recommended DC Operating Conditions
(TA = -25°C to +85°C)
Symbol
VCC
GND
VIH
VIL
CL
TTL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Output Load
Output Load
Min.
2.7
0
2.2
-0.3
-
-
Typ.
3.0
0
-
-
-
-
Max.
3.6
0
VCC + 0.3
+0.6
30
1
Unit
V
V
V
V
pF
-
Absolute Maximum Ratings*
VCC to GND .............................................. -0.5V to +4.6V
IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V
Operating Temperature, Topr ................... -25°C to +85°C
Storage Temperature, Tstg..................... -55°C to +125°C
Temperature Under Bias, Tbias................ -10°C to +85°C
Power Dissipation, PT ...............................................0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -25°C to +85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
ILI Input Leakage Current
LP62S1024B-55LLT/70LLT
Min.
Max.
Unit
Conditions
- 1 µA VIN = GND to VCC
ILO
ICC
Output Leakage Current
Active Power Supply
Current
ICC1
Dynamic Operating
Current
ICC2
-
-
-
-
CE1 = VIH or CE2 = VIL
1 µA or OE = VIH or WE = VIL
VI/O = GND to VCC
3 mA CE1 = VIL, CE2 = VIH
II/O = 0mA
Min. Cycle, Duty = 100%
30 mA CE1 = VIL, CE2 = VIH
II/O = 0mA
CE1 = VIL, CE2 = VIH
3 mA VIH = VCC, VIL = 0V
f = 1 MHZ, II/O = 0mA
PRELIMINARY (October, 2002, Version 0.1)
4
AMIC Technology, Corp.
5 Page 
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
Address
CE1
CE2
WE
DIN
DOUT
(4)
tAS1
(4)
tWC
tAW
tCW5
tCW5
tWP2
tDW
tWHZ7
LP62S1024B-T Series
tWR3
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (October, 2002, Version 0.1)
10
AMIC Technology, Corp.
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet LP62S1024BX-55LLTF.PDF ] | |
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