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PDF LP61L1024X-15 Data sheet ( Hoja de datos )
| Número de pieza | LP61L1024X-15 | |
| Descripción | 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Document Title
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Revision History
Rev. No.
2.0
2.1
History
Add product family and 32-pin TSSOP package
Add 36 ball BGA package type
Issue Date
May 9, 2002
August 22, 2002
Remark
Final
(August, 2002, Version 2.1)
AMIC Technology, Inc.
1 page  
LP61L1024
Truth Table
Mode
Standby
Output Disable
Read
Write
CE1 CE2
HX
XL
LH
LH
LH
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O Operation
High Z
High Z
High Z
DOUT
DIN
Supply Current
ISB, ISB1
ISB, ISB2
ICC1
ICC1
ICC1
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
CI/O*
Parameter
Input Capacitance
Input/Output Capacitance
Min.
Max.
8
10
Unit
pF
pF
Conditions
VIN = 0V
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V + 10, GND = 0V)
Symbol
Parameter
Read Cycle
tRC Read Cycle Time
tAA Address Access Time
tACE1 Chip Enable Access Time
tACE2
tOE
tCLZ1
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ2
tOLZ
tCHZ1
Output Enable to Output in Low Z
Chip Disable to Output in High Z
tCHZ2
tOHZ
tOH
Output Disable to Output in High Z
Output Hold from Address Change
CE1
CE2
CE1
CE2
CE1
CE2
LP61L1024-12
Min.
Max.
12 -
- 12
- 12
- 12
-7
3-
3-
2-
-7
-7
27
3-
LP61L1024-15
Min.
Max.
15 -
- 15
- 15
- 15
-9
5-
5-
2-
- 10
- 10
29
5-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(August, 2002, Version 2.1)
4 AMIC Technology, Inc.
5 Page 
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
LP61L1024
+3.3V
320Ω
I/O
350Ω
30pF*
* Including scope and jig.
+3.3V
320Ω
I/O
350Ω
5pF*
* Including scope and jig.
Figure 1. Output Load
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol
Parameter
Min.
VDR1
VCC for Data Retention
2
VDR2
2
ICCDR1
Data Retention Current
ICCDR2
-
-
tCDR Chip Disable to Data Retention Time 0
tR Operation Recovery Time
5
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Max.
3.6
3.6
5
5
-
-
Unit
V
V
mA
mA
ns
ms
Conditions
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V or
CE2 ≤ 0.2V
CE2 ≤ 0.2V
CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V
VCC = 3.0V
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
VCC = 3.0V
CE2 ≤ 0.2V
CE1 ≤ 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
See Retention Waveform
(August, 2002, Version 2.1)
10 AMIC Technology, Inc.
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LP61L1024X-15.PDF ] | |
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