PDF CY28408 Data sheet ( Hoja de datos )

Número de pieza	CY28408
Descripción	Clock Synthesizer
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY28408 Clock Synthesizer with Differential CPU Outputs Features • Compatible to Intel® CK 408 Mobile Clock Synthesizer • Support Intel P4 and Brookdale CPU • Specifications • 3.3V power supply • Three differential CPU clocks • Ten copies of PCI clocks Table 1. Frequency Table[1] S2 S1 S0 CPU(0:2) 1 0 0 100 MHz 1 0 1 133 MHz 110 1 1 1 166 MHz 0 0 0 66 MHz 0 0 1 100 MHz 010 0 1 1 133 MHz M 0 0 Hi-Z M 0 1 TCLK/2 Block Diagram • Six copies of 3V66 clocks • SMBus support with read back capabilities • Spread Spectrum electromagnetic interference (EMI) reduction • Dial-A-Frequency® features • Dial-A-dB features • 56-pin TSSOP package 3V66 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz Hi-Z TCLK/4 PCI_PCIF 33 MHz 33 MHz Reserved 33 MHz 33 MHz 33 MHz Reserved 33 MHz Hi-Z TCLK/8 REF 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz Hi-Z TCLK USB/DOT 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz Hi-Z TCLK/2 Pin Configuration XIN XOUT CPU_STP# IREF VSSIREF S(0:2) MULT0 VTT_PWRGD# PCI_STP# PLL1 PLL2 PD# SDATA SCLK VDDA WD Logic I2C Logic Power Up Logic REF VDD XIN 1 2 XOUT 3 CPUT(0:2) CPUC(0:2) VSS PCIF0 PCIF1 4 5 6 PCIF2 7 VDD 8 VSS 9 3V66_0 PCI0 EPCI1/PCI1 10 11 3V66_1/VCH PCI2 EPCI3/PCI3 12 13 VDD 14 /2 PCI(0:6) VSS 15 PCI_F(0:2) PCI4 PCI5 16 17 48M_USB PCI6 VDD 18 19 48M_DOT VSS 20 3V66_2 21 3V66_3 22 3V66_4 23 3V66_5 24 PD# 25 3V66[2:5] VDDA 26 VSSA 27 VTT_PWRGD# 28 56 REF 55 S1 54 S0 53 CPU_STP# 52 CPUT0 51 CPUC0 50 VDD 49 CPUT1 48 CPUC1 47 VSS 46 VDD 45 CPUT2 44 CPUC2 43 MULT0 42 IREF 41 VSSIREF 40 S2 39 48M_USB 38 48M_DOT 37 VDD 36 VSS 35 3V66_1/VCH 34 PCI_STP# 33 3V66_0 32 VDD 31 VSS 30 SCLK 29 SDATA Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, an 0 state will be latched into the device’s internal state register. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07617 Rev. Revised December 17, 2003 1 page CY28408 Byte 1: CPU Clock Register (continued) Bit @Pup Name 11 CPUT/C1 01 CPUT/C0 Description CPUT/C1 Output Control 1 = enabled, 0 = three-state CPUT/C1 This is a Read and Write control bit. CPUT/C0 Output Control 1 = enabled, 0 = three-state CPUT/C0 This is a Read and Write control bit. Byte 2: PCI Clock Control Register (all bits are read- and write-functional) Bit @Pup 70 61 51 41 31 21 11 01 Name REF PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Description REF Output Control. 0 = high strength, 1 = low strength PCI6 Output Control 1 = enabled, 0 = forced LOW PCI5 Output Control 1 = enabled, 0 = forced LOW PCI4 Output Control 1 = enabled, 0 = forced LOW PCI3 Output Control 1 = enabled, 0 = forced LOW PCI2 Output Control 1 = enabled, 0 = forced LOW PCI1 Output Control 1 = enabled, 0 = forced LOW PCI0 Output Control 1 = enabled, 0 = forced LOW Byte 3: PCI_F Clock and 48M Control Register (all bits are read- and write-functional) Bit @Pup 71 61 50 40 30 21 11 01 Name 48M_DOT 48M_USB PCI_F2 PCI_F1 PCI_F0 Description 48M_DOT Output Control 1 = enabled, 0 = forced LOW 48M_USB Output Control 1 = enabled, 0 = forced LOW PCI_STP#, control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_STP#, control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_STP#, control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW PCI_F2 Output Control 1 = running, 0 = forced LOW PCI_F1 Output Control 1 = running, 0 = forced LOW PCI_F0 Output Control 1 = running, 0 = forced LOW Document #: 38-07617 Rev. Page 5 of 19 5 Page PD# CPUT CPUC PCI 3V66 48M_USB REF Figure 7. Power-down Assertion Timing Waveforms PD# – Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 1.8 ms. PD# CPUT Tstable <1.8ms CPUC PCI 3V66 48M_USB REF Tdrive_PW RDN# <300µs, >200mV Figure 8. Power-down Assertion Timing Waveforms Table 10.PD# Functionality PD# 3V66 PCI_F 1 66 MHz 33 MHz 0 Low Low PCI 33 MHz Low USB/DOT 48 MHz Low CY28408 Document #: 38-07617 Rev. ** Page 11 of 19 11 Page

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