PDF CY28401 Data sheet ( Hoja de datos )

Número de pieza	CY28401
Descripción	100-MHz Differential Buffer for PCI Express and SATA
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY28401 100-MHz Differential Buffer for PCI Express and SATA Features Functional Description • CK409 or CK410 companion buffer • Eight differential 0.7v clock pairs • Individual OE controls • Low CTC jitter (< 50 ps) • Programmable bandwidth • SRC_STOP# power management control • SMBus Block/Byte/Word Read and Write support • 3.3V operation • PLL Bypass-configurable • Divide by 2 programmable • 48-pin SSOP package The CY28401 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. Block Diagram OE_[0:7] SRC_STOP# PWRDWN# SCLK SDATA SRC_DIV2# PLL/BYPASS# SRCT_IN SRCC_IN HIGH_BW# Output Control SMBus Controller Output Buffer DIV PLL DIFT0 DIFC0 DIFT1 DIFC1 DIFT2 DIFC2 DIFT3 DIFC3 DIFT4 DIFC4 DIFT5 DIFC5 DIFT6 DIFC6 DIFT7 DIFC7 LOCK Pin Configuration SRC_DIV2# VDD VSS SRCT_IN SRCC_IN OE_0 OE_3 DIFT0 DIFCO VSS VDD DIFT1 DIFC1 OE_1 OE_2 DIFT2 DIFC2 VSS VDD DIFT3 DIFC3 PLL/BYPASS# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 VDD_A 47 VSS_A 46 IREF 45 LOCK 44 OE_7 43 OE_4 42 DIFT7 41 DIFC7 40 VSS 39 VDD 38 DIFT6 37 DIFC6 36 OE_6 35 OE_5 34 DIFT5 33 DIFC5 32 VSS 31 VDD 30 DIFT4 29 DIFC4 28 HIGH_BW# 27 SRC_STOP# 26 PWRDWN# 25 VSS 48 SSOP Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07592 Rev. Revised November 24, 2003 1 page Byte 2: Control Register 2 (continued) Bit @pup 20 Name 10 00 Byte 3: Control Register 3 Bit @pup 70 60 50 40 30 20 10 00 Byte 4: Vendor ID Register Bit @Pup 70 60 50 40 31 20 10 00 Byte 5: Control Register 5 Bit @Pup 70 60 50 40 30 20 10 00 Name Name Name CY28401 Description Allow Control DIF_2 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_1 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_0 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Document #: 38-07592 Rev. Page 5 of 14 5 Page CY28401 AC Electrical Specifications (continued) Parameter Description Condition VHIGH Voltage High Measured SE VLOW Voltage Low Measured SE VOX Crossing Point Voltage at 0.7V Swing ∆VOX Vcross Variation over all edges VOVS Maximum Overshoot Voltage VUDS Minimum Undershoot Voltage VRB Ring Back Voltage Measured SE tPD(PLL) Input to output skew in PLL mode Measured at crossing point VOX tPD(NONPLL) Input to output skew in Non–PLL mode Measured at crossing point VOX Min. 660 –150 250 – – – 0.2 – 2.5 Max. Unit 850 mv – mv 550 mv 140 mV VHIGH + 0.3 V –0.3 V N/A V ±250 ps 6.5 ns D IF T 33Ω T PCB 4 9 .9 Ω M easurem ent P o in t 2pF D IF C IR E F 33Ω T PCB 4 9 .9 Ω M easurem ent P o in t 2pF 475Ω T ra c e Im p e d a n c e M e a s u re d D iffe re n tia lly Figure 8. Differential Clock Termination Switching Waveforms VOH = 0.525V VCROSS TRise (CLOCK) CLOCK# CLOCK VOL = 0.175V TFall (CLOCK) Figure 9. Single-Ended Measurement Points for TRise and TFall Document #: 38-07592 Rev. ** Page 11 of 14 11 Page

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