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PDF HI3197 Data sheet ( Hoja de datos )
| Número de pieza | HI3197 | |
| Descripción | 125 MSPS D/A Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HI3197
October 1998 File Number 4356.1
10-Bit, 125 MSPS D/A Converter
The HI3197 is a high-speed D/A converter which can
perform the multiplexed input of the two system 10-bit data.
The maximum conversion rate achieves 125 MSPS. The
multiplexed operation is possible by the 1/2 frequency-
divided clock or by halving the frequency of the clock with
the clock frequency divider circuit having the reset pin in
the IC. The data input is TTL; the clock input pin and reset
input pin can select either TTL or PECL according to the
application.
Ordering Information
PART NUMBER
HI3197JCQ
TEMP.
RANGE (oC) PACKAGE
-20 to 75 48 Ld MQFP/
PQFP
PKG. NO.
Q48.7x7-S
Features
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits
• Conversion Rate
125 MSPS (PECL)
100 MSPS (TTL)
• Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL
• Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ)
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s
• Clock, Reset Input Level: TTL and PECL Compatible 2:1
Multiplexed Input Function
• 1/2 Frequency-Divided Clock Output Possible by the Built-
In Clock Frequency Divider Circuit
• Voltage Output (50Ω Load Drive Possible)
• Single Power Supply or ±Dual Power Supplies
• Polarity Switching Function of Reset Signal
Applications
• LCD
• DDS
• HDTV
• Communications (QPSK, QAM)
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Pinout
HI3197 (MQFP)
TOP VIEW
AGND2
VOCLP
R POLARITY
INV
PS
DVCC1
NC
DGND1
(MSB) DA9
DA8
DA7
DA6
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 21
41 20
42 19
43 18
44 17
45 16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
RESETN/E
RESETP/E
RESET/T
CLKN/E
CLKP/E
CLK/T
DIV2OUT
DIV2IN
DB0 (LSB)
DB1
DB2
DB3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page  
HI3197
Pin Descriptions and I/O Pin Equivalent Circuits (Continued)
PIN NO
34
SYMBOL
VREF
TYPICAL
VOLTAGE
I/O LEVEL
O AGND +1.2V
EQUIVALENT CIRCUIT
AVCC2
34
DESCRIPTION
Analog Reference Voltage Output.
35
VSET
I AGND2 + 0.7V to
AGND2 + 1.03V
AVCC2
35
36
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37
38
AVCC2
AGND2
VOCLP
Single Power
Supply: +5V
Dual Power
Supplies: GND
Single Power
Supply: GND
Dual Power
Supplies: -5V
I Clamp Voltage
39 P Polarity I TTL
5
DVCC1
39
DGND1
AGND2
Full scale adjustment.
Analog Power Supply.
Analog Power Supply
DVCC1
38
TTL Output High Level Clamp. The
TTL level signal is output from the
DIV2OUT pin for MUX.1A mode.
The TTL high level voltage is
clamped to the value approximate-
ly equivalent to the voltage sup-
plied to this pin. Leave the VOCLP
pin open for other modes.
DGND1
Reset signal polarity switching. At
high level, the reset polarity is ac-
tive high; at low level, active low.
VREF
5 Page 
HI3197
Electrical Characteristics Measurement Circuits (Continued)
+5V
10
HIGH FOR ALL SIDE A DATA
10
LOW FOR ALL SIDE B DATA
1MHz TTL CLK
+5V
I1 I2 I3 I4
DVCC1 DVCC2 AVCC2 AVCC0
DA0
TO
DA9
DB0
TO
DB9
CLK/T
AOUTP
HI3197
AOUTN
VSET
DIV2IN
DIV2OUT
PS
C1 C2 C3
DGND1
DGND2
AGND2
ICC = I1 + I2 + I3 + I4
DICC1 = I1
DICC2 = I2
ALCC2 = I3
ALCC0 = I4
937.5mV
FIGURE 2. CURRENT CONSUMPTION
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+5V
10
HIGH FOR ALL SIDE A DATA
10
LOW FOR ALL SIDE B DATA
1MHz TTL CLK
+5V
DVCC1
DA0
TO
DA9
DGND1
DVCC2
AVCC2
AVCC0
AOUTP
DB0
TO
DB9
CLK/T
HI3197
AOUTN
PS DGND2 VSET
C1 C2 C3 AGND2
-5V
+5V
V
50Ω
V
50Ω
937.5mV
-5V
FIGURE 3. ANALOG OUTPUT CHARACTERISITCS, OUTPUT FULL-SCALE ABSOLUTE AMPLITUDE ERROR, OUTPUT ZERO OFFSET
VOLTAGE
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet HI3197.PDF ] | |
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