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PDF IS42S16100A1 Data sheet ( Hoja de datos )
| Número de pieza | IS42S16100A1 | |
| Descripción | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM | |
| Fabricantes | ISSI | |
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IS42S16100A1
ISSI®
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
August 2003
FEATURES
• Clock frequency: 166, 143, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
•www.DataSheet4U.com Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II
• Lead-free package option
PIN DESCRIPTIONS
A0-A11
A0-A10
A11
A0-A7
DQ0 to DQ15
CLK
CKE
CS
RAS
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data DQ
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100A1 is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 GND
49 DQ15
48 IDQ14
47 GNDQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 GNDQ
40 DQ9
39 DQ8
38 VDDQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 GND
CAS
WE
LDQM
UDQM
VDD
GND
VDDQ
GNDQ
NC
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
08/12/03
1
1 page  
IS42S16100A1
ISSI ®
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL Input Leakage Current 0V ≤ VIN ≤ VDD, with pins other than
the tested pin at 0V
–5 5 µA
IOL Output Leakage Current Output is disabled, 0V ≤ VOUT ≤ VDD
–5 5 µA
VOH Output High Voltage Level IOUT = –2 mA
2.4 —
V
VOL Output Low Voltage Level IOUT = +2 mA
— 0.4
V
ICC1 Operating Current(1,2)
One Bank Operation,
Burst Length=1
tRC ≥ tRC (min.)
IOUT = 0mA
CAS latency = 3
Com.
Ind.
Com.
Ind.
-6
-7
-7
-10
-10
— 160 mA
— 140 mA
— 160 mA
— 120 mA
— 140 mA
ICC2P Precharge Standby Current CKE ≤ VIL (MAX)
ICC2PS (In Power-Down Mode)
tCK = tCK (MIN) Com.
Ind.
tCK = ∞
Com.
Ind.
—
—
—
—
—
—
—
—
3 mA
4 mA
2 mA
3 mA
ICC3N
ICC3NS
Active Standby Current CKE ≥ VIH (MIN)
(In Non Power-Down Mode)
tCK = tCK (MIN)
— — 40 mA
tCK = ∞
Com. — — 30 mA
Ind. — — 30 mA
ICC4 Operating Current
(In Burst Mode)(1)
tCK = tCK (MIN)
IOUT = 0mA
CAS latency = 3
Com.
Ind.
-6
-7
-7
— 150 mA
— 130 mA
— 150 mA
Com. -10 — 140 mA
Ind. -10 — 160 mA
CAS latency = 2
-6 — 150 mA
Com. -7
— 130 mA
Ind. -7
— 150 mA
Com. -10 — 140 mA
Ind. -10 — 160 mA
ICC5 Auto-Refresh Current
tRC = tRC (MIN)
CAS latency = 3
Com.
-6
-7
— 100 mA
— 70 mA
Ind. -7
— 90 mA
Com. -10 — 140 mA
Ind. -10 — 160 mA
CAS latency = 2
-6 — 100 mA
Com. -7
— 70 mA
Ind. -7
Com. -10
— 90 mA
— 140 mA
Ind. -10 — 160 mA
ICC6 Self-Refresh Current
CKE ≤ 0.2V
— -— 1 mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between VDD and GND for each
memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
08/12/03
5
5 Page 
IS42S16100A1
ISSI ®
Mode Register Set Command
(CS, RAS, CAS, WE = LOW)
The IS42S16100A1 product incorporates a register that
defines the device operating mode. This command
functions as a data input pin that loads this register from
the pins A0 to A11. When power is first applied, the
stipulated power-on sequence should be executed and
then the IS42S16100A1 should be initialized by executing
a mode register set command.
Note that the mode register set command can be executed
only when both banks are in the idle state (i.e. deactivated).
Another command cannot be executed after a mode
register set command until after the passage of the period
tMCD, which is the period required for mode register set
command execution.
Active Command
(CS, RAS = LOW, CAS, WE= HIGH)
The IS42S16100A1 includes two banks of 4096 rows each.
This command selects one of the two banks according to
the A11 pin and activates the row selected by the pins A0
to A10.
This command corresponds to the fall of the RAS signal
from HIGH to LOW in conventional DRAMs.
When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
When the A10 pin is LOW, the bank selected by the A11 pin
remains in the activated state after the burst read completes.
Write Command
(CS, CAS, WE = LOW, RAS = HIGH)
When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
at the start address specified by pins A0 to A9. This first
data must be input to the DQ pins in the cycle in which this
command.
The selected bank must be activated before executing this
command.
When A10 pin is HIGH, this command functions as a write
with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11 pin
remains in the activated state after the burst write completes.
After the input of the last burst write data, the application
must wait for the write recovery period (tDPL, tDAL) to elapse
according to CAS latency.
Precharge Command
(CS, RAS, WE = LOW, CAS = HIGH)
This command starts precharging the bank selected by
pins A10 and A11. When A10 is HIGH, both banks are
precharged at the same time. When A10 is LOW, the bank
selected by A11 is precharged. After executing this
command, the next command for the selected bank(s) is
executed after passage of the period tRP, which is the
period required for bank precharging.
This command corresponds to the RAS signal from LOW
to HIGH in conventional DRAMs
Read Command
(CS, CAS = LOW, RAS, WE = HIGH)
This command selects the bank specified by the A11 pin
and starts a burst read operation at the start address
specified by pins A0 to A9. Data is output following CAS
latency.
The selected bank must be activated before executing
this command.
Auto-Refresh Command
(CS, RAS, CAS = LOW, WE, CKE = HIGH)
This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generated during this operation.
Both banks must be placed in the idle state before executing
this command.
The stipulated period (tRC) is required for a single refresh
operation, and no other commands can be executed during
this period.
The device goes to the idle state after the internal refresh
operation completes.
This command must be executed at least 4096 times every
128 ms.
This command corresponds to CBR auto-refresh in
conventional DRAMs.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
08/12/03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS42S16100A1.PDF ] | |
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