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PDF TMP470R1B512 Data sheet ( Hoja de datos )
| Número de pieza | TMP470R1B512 | |
| Descripción | 16/32-Bit RISC Flash Microcontroller | |
| Fabricantes | Analog Devices | |
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FEATURES
• High-Performance Static CMOS Technology
• TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
– 24-MHz System Clock (60-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Utilizes Big-Endian Format
• Integrated Memory
– 512K-Byte Program Flash
• 2 Banks With 14 Contiguous Sectors
• Internal State Machine for Programming
and Erase
– 32K-Byte Static RAM (SRAM)
• 27 Dedicated General-Purpose Input/Output
(GIO) Pins, 1 Input-Only GIO Pin, and 59
Additional Peripheral I/Os
• Operating Features
– Core Supply Voltage (VCC): 1.81 V – 2.05 V
– I/O Supply Voltage (VCCIO): 3.0 V – 3.6 V
– Low-Power Modes: STANDBY and HALT
– Extended Industrial Temperature Range
• 470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
– Interrupt Expansion Module (IEM)
• Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
• Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
• External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
• Seven Communication Interfaces:
– Three Serial Peripheral Interfaces (SPIs)
• 255 Programmable Baud Rates
– Two Serial Communications Interfaces
(SCIs)
• 224 Selectable Baud Rates
• Asynchronous/Isosynchronous Modes
• Two High-End CAN Controllers (HECCs)
• 32-Mailbox Capacity Each
• Fully Compliant With CAN Protocol,
Version 2.0B
• High-End Timer (HET)
– 32 Programmable I/O Channels:
• 24 High-Resolution Pins
• 8 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
• 128-Instruction Capacity
• 16-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 128-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 µs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
• Eight External Interrupts
• Flexible Interrupt Handling
• On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1(1) (JTAG) Test-Access Port
• 144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
(1) The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture specification. Boundary scan is not
supported on this device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
Copyright © 2005–2006, Texas Instruments Incorporated
1 page  
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TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
Device Characteristics
The B512 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all the
characteristics of the B512 device except the SYSTEM and CPU, which are generic.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1B512
COMMENTS
MEMORY
For the number of memory selects on this device, see Table 3, Memory Selection Assignment.
INTERNAL MEMORY
Pipeline/Non-Pipeline
512K-Byte flash
32K-Byte SRAM
Flash is pipeline-capable.
The B512 RAM is implemented in one 32K array selected by two
memory-select signals (see Table 3, Memory Selection Assignment).
PERIPHERALS
For the device-specific interrupt priority configurations, see Table 7, Interrupt Priority (IEM and CIM). And for the 1K peripheral address
ranges and their peripheral selects, see Table 5, A512 Peripherals, System Module, and Flash Base Addresses.
CLOCK
ZPLL
Zero-pin PLL has no external loop filter pins.
GENERAL-PURPOSE I/Os
27 I/O
1 Input only
Ports A, B, and C each have eight (8) external pins.
Port D has four (4) external pins.
ECP
YES
SCI
2 (3-pin)
SCI1 and SCI2
CAN
(HECC and/or SCC)
2 HECCs
Two high-end CAN controller modules (HECC1 and HECC2)
SPI
(5-pin, 4-pin or 3-pin)
3 (5-pin)
SPI1, SPI2, and SPI3
The B512 device has both the logic and registers for a full 32-I/O HET
implemented and all 32 pins are available externally.
HET with XOR Share
32 I/O
The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent
of whether or not the odd pin is available externally. If an odd pin is
available externally and shared, then the odd pin can only be used as a
general-purpose I/O. For more information on HR SHARE, see the
TMS470R1x High-End Timer (HET) Reference Guide (literature number
SPNU199).
HET RAM
128-Instruction Capacity
MibADC
10-bit, 16-channel 128-word The B512 device has both the logic and registers for a full 16-channel
FIFO
MibADC implemented and all 16 pins are available externally.
CORE VOLTAGE
1.81 – 2.05 V
I/O VOLTAGE
3.0 – 3.6 V
PINS
144
PACKAGE
PGE
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TERMINAL
NAME
NO.
VCCIO
VSS
VSSIO
17
53
82
11
30
54
85
92
127
131
136
16
52
81
TYPE (1) (2)
TMS470R1B512
16/32-Bit RISC Flash Microcontroller
SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006
Table 2. Terminal Functions (continued)
INTERNAL
PULLUP/
PULLDOWN (3)
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
DESCRIPTION
3.3-V PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
GND
Core supply ground reference
GND
SUPPLY GROUND DIGITAL I/O
Digital I/O supply ground reference
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