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PDF TQPHT Data sheet ( Hoja de datos )

Número de pieza TQPHT
Descripción pHEMT Foundry Service
Fabricantes TriQuint Semiconductor 
Logotipo TriQuint Semiconductor Logotipo



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Production Process
TQPHT
0.5 um pHEMT Foundry Service
Nitride
Metal 2
Metal 2 - 4um
Dielectric
Dielectric
Metal 1
Metal 1
Dielectric
MIM Metal
Metal 0
Metal 1 - 2um
NiCr
N+ Pseudomorphic
Channel
pHEMT
IsoIlasotiloantiIomnpIlmanptlant
MIM Capacitor
NiCr Resistor
Semi-Insulating GaAs Substrate
www.DataSheet4U.com
0.5 um pHEMT Device Cross-Section
Features
D-Mode, -0.8 V Vp
InGaAs Active Layer pHEMT
Process
0.5 um Optical Lithography
Gates
17 V D-G Breakdown Voltage
High Density Interconnects:
2 Global
1 Local
High-Q Passives
Thin Film Resistors
High Value Capacitors
Backside Vias Optional
Based on Production 0.25 µm
pHEMT and Passives Processes
TOM3 FET Models Available
General Description
TriQuint’s 0.5 µm pHEMT process is based on our production
released 0.25 µm gate process. TQPHT substitutes lower cost
optical lithography in place of e-beam and adds TriQuint’s
unique thick metal scheme. This process is targeted for high
efficiency and linearity in power amplifiers, low noise amplifiers,
and linear, low loss and high isolation RF switch applications.
The TQPHT process offers a D-Mode pHEMT with a –0.8 V
pinch off. The three metal interconnecting layers are encapsu-
lated in a high performance dielectric that allows wiring flexibil-
ity, optimized die size and plastic packaging simplicity. Precision
NiCr resistors and high value MIM capacitors are included al-
lowing higher levels of integration, while maintaining smaller,
cost –effective die sizes.
Applications
Highly Efficient and Linear
Power Amplifiers
Low Loss, High Isolation
Switches for Wireless Trans-
ceivers and Basestations
Higher Supply Voltage Applica-
tions
Integrated RF Front Ends–
LNA, SW, PA
Fully Released
Production Process
Page 1 of 5; Rev 2.0 7/22/03

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TQPHT pdf
Production Process
TQPHT
0.5 um pHEMT Foundry Service
Prototyping and Development
Prototype Development Quick Turn (PDQ):
Shared mask set
Run monthly
Hot Lot cycle time
Prototype Wafer Option (PWO):
Customer-specific masks; Customer schedule
2 wafers delivered
Hot Lot cycle time
With thinning and sawing; optional backside
vias
Design Tool Status
Complete Design Manual Now
Device Library of circuit elements: FETs, diodes, thin
film resistors, capacitors, inductors
Design Kit for Agilent’s ADS design environment
Design Kit planned for AWR Microwave Office
Layout Library in GSD II format
Cadence Development Kit with PCells
Layout Rule Sets for Design Rule Check
Qualified package models for supported package styles
Training
GaAs Design Classes:
Half-Day Introduction; Upon request
Four-Day Technical Training; Fall and Spring at
TriQuint Oregon facility
For Training & PDQ Schedules, please visit:
www.triquint.com/foundry/
Process Qualification Status
Mature process based on TQTx, 150-mm process
Process released to production
Full 150mm wafer Process Qualification complete
For more information on Quality and Reliability, con-
tact TriQuint or visit:
www.triquint.com/manufacturing/QR/
Applications Support Services
Tiling of GDSII stream files including PCM
Design Rule Check services
Layout Versus Schematic check services
Packaging Development Engineering
Test Development Engineering:
On-wafer
Packaged parts
Thermal Analysis Engineering
Yield Enhancement Engineering
Part Qualification Services
Failure Analysis
Manufacturing Services
Mask making
Production 150-mm wafer fab
Wafer Thinning
Wafer Sawing
Substrate Vias
DC Diesort Testing
RF On-wafer testing
Plastic Packaging
RF Packaged Part Testing
Please contact your local TriQuint Semiconductor Representative/ Distributor
or Foundry Services Division for Additional information:
E-mail: [email protected] Phone: (503) 615-9000 Fax: (503) 615-8905
TriQuint Semiconductor
2300 NE Brookwood Pkwy
Hillsboro, Oregon 97124
Semiconductors for Communications
www.triquint.com
Page 5 of 5; Rev 2.0 7/22/03
Phone: 503-615-9000
Fax: 503-615-8905

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