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PDF DS90C241 Data sheet ( Hoja de datos )
| Número de pieza | DS90C241 | |
| Descripción | (DS90C124 / DS90C241) 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2006
www.DataSheet4U.com
DS90C241/DS90C124
5-35MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS90C241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream sim-
plifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and connector
size and pins.
The DS90C241/124 incorporates LVDS signaling on the
high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the serializer output edge rate
for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
Features
n 5 MHz–35 MHz clock embedded and DC-Balancing
24:1 and 1:24 data transmissions
n User defined Pre-Emphasis driving ability through
external resistor on LVDS outputs and capable to drive
up to 10 meters shielded twisted-pair cable
n User selectable clock edge for parallel data on both
Transmitter and Receiver
n Internal DC Balancing encode/decode – Supports
AC-coupling interface with no external coding required
n Individual power-down controls for both Transmitter and
Receiver
n Embedded clock CDR (clock and data recovery) on
Receiver and no external source of reference clock
needed
n All codes RDL (random data lock) to support
hot-pluggable applications
n LOCK output flag to ensure data integrity at Receiver
side
n Balanced TSETUP/THOLD between RCLK and RDATA on
Receiver side
n PTO (progressive turn-on) LVCMOS outputs to reduce
EMI and minimize SSO effects
n All LVCMOS inputs and control pins have internal
pulldown
n On-chip filters for PLLs on Transmitter and Receiver
n 48-pin TQFP package
n Pure CMOS .35 µm process
n Power supply range 3.3V ± 10%
n Temperature range –40˚C to +105˚C
n 8 kV HBM ESD structure
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation DS201719
20171901
www.national.com
1 page  
Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
tHZR
HIGH to TRI-STATE Delay (Figure 12)
ROUT [23:0],
tLZR LOW to TRI-STATE Delay
RCLK, LOCK
tZHR
TRI-STATE to HIGH Delay
tZLR TRI-STATE to LOW Delay
tDD
Deserializer Delay
(Figure 10)
RCLK
tDRDL
RxIN_TOL_L
RxIN_TOL_R
Deserializer PLL Lock Time
from Powerdown
Receiver INput TOLerance
Left,
Receiver INput TOLerance
Right,
(Figure 13)
(Notes 7, 8)
(Figure 15)
(Notes 6, 8, 10)
(Figure 15)
(Notes 6, 8, 10)
5 MHz
35 MHz
5 MHz–35 MHz
5 MHz–35 MHz
Typ
3
3
3
3
[4+(3/56)]T
+5.9
5
5
Max Units
10 ns
10 ns
10 ns
10 ns
[4+(3/56)]T ns
+14
50 ms
50 ms
0.25
UI
0.25
UI
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: tDRDL is the time required by the deserializer to obtain lock when exiting powerdown mode. tDRDL is specified with an external synchronization pattern.
Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.
Note 8: Parameter is guaranteed by design and characterization using statistical analysis.
Note 9: tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
Note 10: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 11: Figures 1, 2, 9, 10, 13 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 12: Figures 6, 11 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 13: TxOUT_E_O is affected by pre-emphasis value.
5 www.national.com
5 Page 
AC Timing Diagrams and Test Circuits (Continued)
FIGURE 13. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
20171914
20171915
FIGURE 14. Transmitter Output Eye Opening (TxOUT_E_O)
11 www.national.com
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet DS90C241.PDF ] | |
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