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PDF CS42418 Data sheet ( Hoja de datos )
| Número de pieza | CS42418 | |
| Descripción | Surround-sound Codecs | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS42418 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CS42418
110 dB, 192 kHz 8-Ch Codec with PLL
Features
! Eight 24-bit D/A, two 24-bit A/D Converters
! 110 dB DAC / 114 dB ADC Dynamic Range
! -100 dB THD+N
! System Sampling Rates up to 192 kHz
! Integrated Low-Jitter PLL for Increased System
Jitter Tolerance
! PLL Clock or System Clock Selection
! 7 Configurable General-Purpose Outputs
! ADC High-Pass Filter for DC Offset Calibration
! Expandable ADC Channels and One-Line
Mode Support
! Digital Output Volume Control with Soft Ramp
! Digital +/-15 dB Input Gain Adjust for ADC
! Differential Analog Architecture
!www.DataSheet4U.com Supports Logic Levels between 1.8 V and 5 V
General Description
The CS42418 codec provides two analog-to-digital and
eight digital-to-analog delta-sigma converters, as well
as an integrated PLL.
The CS42418 integrated PLL provides a low-jitter sys-
tem clock. The internal stereo ADC is capable of
independent channel gain control for single-ended or
differential analog inputs. All eight channels of DAC pro-
vide digital volume control and differential analog
outputs. The general-purpose outputs may be driven
high or low, or mapped to a variety of DAC mute con-
trols or ADC overflow indicators.
The CS42418 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, digital speaker and
automotive audio systems.
The CS42418 is available in a 64-pin LQFP package in
both Commercial (-10° to 70° C) and Automotive
(-40° to 85° C) grades. The CDB42428 Customer Dem-
onstration board is also available for device evaluation.
Refer to “Ordering Information” on page 71.
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
MUTEC
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
VA AGND
GPO
ADC#1
ADC#2
REFGND VQ FILT+ OMCK
RMCK LPFLT VLC DGND VD
Mute
Internal Voltage
Reference
Mult/Div
PLL
Control
Port
INT
RST
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
Digital Filter
Digital Filter
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
Gain & Clip
Gain & Clip
ADC
Serial
Audio
Port
ADCIN1
ADCIN2
ADC_SDOUT
ADC_LRCK
ADC_SCLK
VLS
DAC_LRCK
DAC_SCLK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
NOVEMBER '05
DS603F1
1 page  
CS42418
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 24
Table 2. Common PLL Output Clock Frequencies..................................................................................... 24
Table 3. Slave Mode Clock Ratios ............................................................................................................. 25
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26
Table 5. DAC De-Emphasis ....................................................................................................................... 44
Table 6. Digital Interface Formats .............................................................................................................. 45
Table 7. ADC One-Line Mode.................................................................................................................... 45
Table 8. DAC One-Line Mode.................................................................................................................... 45
Table 9. RMCK Divider Settings ................................................................................................................ 48
Table 10. OMCK Frequency Settings ........................................................................................................ 48
Table 11. Master Clock Source Select....................................................................................................... 49
Table 12. PLL Clock Frequency Detection................................................................................................. 50
Table 13. Example Digital Volume Settings ............................................................................................... 53
Table 14. ATAPI Decode ........................................................................................................................... 54
Table 15. Example ADC Input Gain Settings ............................................................................................. 55
Table 16. PLL External Component Values ............................................................................................... 62
www.DataSheet4U.com
DS603F1
5
5 Page 
CS42418
SWITCHING CHARACTERISTICS
(For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C;
VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, CL = 30 pF)
Parameters
Symbol
RST Pin Low Pulse Width
(Note 12)
PLL Clock Recovery Sample Rate Range
RMCK Output Jitter
(Note 14)
RMCK Output Duty Cycle
(Note 15)
OMCK Frequency
(Note 13)
OMCK Duty Cycle
(Note 13)
DAC_SCLK, ADC_SCLK Duty Cycle
DAC_LRCK, ADC_LRCK Duty Cycle
Master Mode
RMCK to DAC_SCLK, ADC_SCLK active edge delay
RMCK to DAC_LRCK, ADC_LRCK delay
Slave Mode
tsmd
tlmd
Min
1
30
-
45
1.024
40
45
45
0
0
Typ Max Units
- - ms
- 200 kHz
200 - ps RMS
50 55 %
-
25.600
MHz
50 60 %
50 55 %
50 55 %
- 15 ns
- 15 ns
DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT,
ADC_SDOUT Output Valid
DAC_LRCK, ADC_LRCK Edge to MSB Valid
DAC_SDIN Setup Time Before DAC_SCLK Rising Edge
DAC_SDIN Hold Time After DAC_SCLK Rising Edge
DAC_SCLK, ADC_SCLK High Time
www.DataSheet4U.com DAC_SCLK, ADC_SCLK Low Time
DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK
Edge
tdpd
tlrpd
tds
tdh
tsckh
tsckl
tlrck
10
30
20
20
-25
-
(Note 16)
ns
- 26.5 ns
- - ns
- - ns
- - ns
- - ns
- +25 ns
Notes:
12. After powering-up the CS42418, RST should be held low after the power supplies and clocks are set-
tled.
13. See Table 1 on page 24 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2.
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
DAC_SCLK
ADC_SCLK
(output)
DAC_LRCK
ADC_LRCK
(output)
RMCK
t smd
t lmd
DAC_LRCK
ADC_LRCK
(input)
DAC_SCLK
ADC_SCLK
(input)
t lrckd
t lrcks
t sckh
tsckl
DAC_SDINx
ADC_SDOUT
tlrpd tds
tdh
MSB
tdpd
MSB-1
Figure 1. Serial Audio Port Master Mode Timing
DS603F1
Figure 2. Serial Audio Port Slave Mode Timing
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS42418.PDF ] | |
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