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PDF CX28985 Data sheet ( Hoja de datos )

Número de pieza CX28985
Descripción Octal G.Shdsl Transceiver
Fabricantes Mindspeed Technologies　
Logotipo Mindspeed Technologies Logotipo



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Preliminary Information
This document contains information on a new product. The parametric information, although not
fully characterized, is the result of testing initial devices.
CX28985
Octal ZipWireMulti G.shdsl Transceiver with Embedded
Microprocessor
www.DataSheet4U.com
Multi-Mode Operation: G.shdsl+, HDSL2, SDSL, HDSL, and IDSL
The ZipWireMulti DSL solution goes beyond simple compliance with the ITU G.shdsl
standard by supporting the optional Enhanced Performance Asymmetrical PSD (EPAP)
modes of operation. In addition, it is compliant with the ANSI HDSL2 standard (ANSI
T1.418) and provides interoperability with Conexant’s market-leading ZipWire
transceivers through operation in 2B1Q multi-rate mode. The 2B1Q mode includes
support of AutoBaud for SDSL interoperability, rate optimization, fast connect times,
and standards-based HDSL operation. Furthermore, it operates in IDSL mode for
Distinguishing Features
• Multimode operation including:
– ITU G.shdsl including EPAP
modes (ITU G.991.2)
– ITU G.handshake (ITU G.994.1)
– HDSL2 (ANSI T1.418)
– SDSL/2B1Q (AutoBaud)
– HDSL (ITU G.991.1, ETS 101 135
and ANSI TR-28)
interoperability with Basic Rate ISDN repeaters. The ZipWireMulti also supports
Conexant’s own proprietary modes, such as 32-PAM, 64 kbps, and 3.088 Mbps
operation, which provide enhanced spectral compatibility, extended subscriber line
reach, and high-speed operation. All these modes are supported by a single hardware
circuit (i.e., one transformer, crystal, and hybrid for all modes) and can be configured in
realtime via software control.
(Continued)
– IDSL (ANSI T1.601)
– Proprietary/Extended Reach
(ANSI spectrum management for
loop transmission systems)
– Proprietary/high-speed (ANSI
spectrum management for loop
transmission systems)
Functional Block Diagram
• Low power consumption of under
1 W at 2320 kbps, which includes the
AFE and line driver dissipation
Host Bus Interface
• Highly integrated solution including
framer, microprocessor, ROM/RAM,
frequency synthesizer, DSP, AFE, and
line driver
Host
Port
RAM
Internal
RAM
Boot
ROM
RAM
Controller
Expansion
Bus
SDRAM
SRAM
PROM
• Embedded microprocessor for
autonomous operation and EOC
processing
Serial • Data rates from 64 kbps to
3.088 Mbps in 8 kbps increments
PCM
Serial Data
PCM
Serial Data
PCM
Serial Data
PCM
Serial Data
DSL
Framer
DSL
Framer
DSL
Framer
DSL
Framer
DSL
Serial Data
DSL
Serial Data
DSL
Serial Data
DSL
Serial Data
DSP
DSP
DSP
DSP
AFE
Serial Interface
AFE
Serial Interface
AFE
Serial Interface
AFE
Serial Interface
ZipWireMulti
AFE and
Line Driver
Copper
Pair
Copper
Pair
Copper
Pair
Copper
Pair
• Interoperability with ZipWire 2B1Q
transceivers including AutoBaud
• Simultaneous operation of UTOPIA
Level 2 and PCM interfaces on a
per-channel basis
• Central office (COT) and remote (RT)
operation
• Individual clock recover circuits per
channel
• Fast warm startup
UTOPIA
/PCM
/DSL
PCM
Serial Data
PCM
Serial Data
PCM
Serial Data
DSL
Framer
DSL
Framer
DSL
Framer
DSL
Serial Data
DSL
Serial Data
DSL
Serial Data
DSP
DSP
DSP
AFE
Serial Interface
AFE
Serial Interface
AFE
Serial Interface
ZipWireMulti
AFE and
Line Driver
Copper
Pair
Copper
Pair
Copper
Pair
• Glueless interface to popular
microprocessors
• Single hardware circuit supports all
speeds and modes of operation
• +1.8 V, +3.3 V and +12 V power
supplies
• JTAG boundary scan
PCM
Serial Data
DSL
Framer
DSL
Serial Data
DSP
AFE
Serial Interface
Copper
Pair
•
ZipWireMulti DSP, Framer, and µP
Data Sheet
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary and Confidential
500015A
February 2001

1 page




CX28985 pdf
Table of Contents
www.DataSheet4U.com
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
1.0 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.3 ZipWireMulti Transceiver/Framer Functional Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.1 The ZipWireMulti ARM Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.2 ZipWireMulti Transceiver/DSP Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 ZipWireMulti G.handshake Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5 ZipWireMulti DSL Framer Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6 ZipWireMulti AFE Functional Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.7 ZipWireMulti ATM Phy Transmission Convergence Functional Summary. . . . . . . . . . . . . . . . . 1-10
1.8 ZipWireMulti General Multiplexing Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.9 ZipWireMulti Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.10 ZipWireMulti Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
2.0 Application Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Eight Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Framer Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 ZipWireMulti Transceiver/Framer to Bt8370 T1/E1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 DSL Framer to Bt8474 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
500015A
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary and Confidential
v

5 Page





CX28985 arduino
CX28985
Octal ZipWireMulti G.shdsl Transceiver with Embedded Microprocessor
List of Tables
List of Tables
www.DataSheet4U.com
Table 3-1.
Table 3-2.
Table 4-1.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 5-10.
Table 5-11.
Table 5-12.
Table 5-13.
Table 5-14.
Table 5-15.
Table 5-16.
Table 5-17.
Table 5-18.
Table 5-19.
Table 5-20.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Table 7-7.
Table 7-8.
Table 7-9.
Clocking Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
CX28985 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Multi-frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
ZipWireMulti Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Recommended Hardware Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Host Bus Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Host TX FIFO Data—Write HBA[8:0] = 0x100–0x1FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Host RX FIFO Data—Read HBA = 0x100–0x1FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Host FIFO Control Register—Read/Write HBA = 0x000 {default 0x19} . . . . . . . . . . . . . . . . 5-14
Host FIFO Interrupt Status Register—Read HBA = 0x004 {default 0x300} . . . . . . . . . . . . . 5-14
Host FIFO Interrupt Acknowledge Register—Write HBA = 0x004 . . . . . . . . . . . . . . . . . . . . 5-15
Host TX FIFO Size—Read HBA = 0x010 {default 0x0} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Host TX FIFO High Threshold—Read/Write HBA = 0x014 {default 0xF3} . . . . . . . . . . . . . . 5-15
Host TX FIFO Low Threshold—Read/Write HBA = 0x018 {default 0x40}. . . . . . . . . . . . . . . 5-15
Host RX FIFO Size—Read HBA = 0x020 {default 0x0}. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Host RX FIFO High Threshold—Read/Write HBA = 0x024 {default 0xC0} . . . . . . . . . . . . . . 5-16
Host RX FIFO Low Threshold—Read/Write HBA = 0x028 {default 0x0D} . . . . . . . . . . . . . . 5-16
HBCFG—Read/Write HBA = 0x070 {default 0x00}. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Typical SDRAMs +3.3 V 64-Mb (2 M ¥ 32 Bits Wide) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
ZipWireMulti AFE Compensation Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
ZipWireMulti AFE Bias Current Network Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
CX28985 DSP/Framer Single Mode Ball Assignment (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . 6-2
CX28985 DSP/Framer Multi-Mode Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
CX28985 DSP/Framer Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
CX28985 DSP/Framer No Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Pin List for 28985 Single Channel AFE/Line Drive—Alphabetic Order. . . . . . . . . . . . . . . . . . 6-8
ZipWireMulti Transceiver/Framer Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
ZipWireMulti AFE Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Transceiver/Framer DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Host Processor Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Input Clock Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Input Setup and Hold Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Output Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
UTOPIA Transmit Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
UTOPIA Receive Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
500015A
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary and Confidential
xiii

11 Page







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