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PDF BUF20820 Data sheet ( Hoja de datos )
| Número de pieza | BUF20820 | |
| Descripción | 18-Channel GAMMA VOLTAGE GENERATOR | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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BUF20820
SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006
18-Channel GAMMA VOLTAGE GENERATOR
with Two Programmable VCOM Channels
FEATURES
D 18-CHANNEL GAMMA CORRECTION
D 2-CHANNEL PROGRAMMABLE VCOM:
100mA IOUT
D ON-CHIP OTP MEMORY
D 10-BIT RESOLUTION
D RAIL-TO-RAIL OUTPUT
D LOW SUPPLY CURRENT: 900µA/ch
D SUPPLY VOLTAGE: 7V to 18V
D DIGITAL SUPPLY: 2.0V to 5.5V
D INDUSTRY-STANDARD, TWO-WIRE
INTERFACE: 3.4MHz HIGH-SPEED MODE
D HIGH ESD RATING:
4kV HBM, 1kV CDM, 200V MM
D DEMO BOARD AND SOFTWARE AVAILABLE
www.DataSheet4U.com
2V−5.5V
Digital
BUF20820
7V−18V
Analog
REFH
SDA
SCL
Control IF
LD AO
REFH OUT
OUT 1
OUT 2
18 Output Channels plus
Two VCOM Channels
OUT 17
OUT 18
VCOM OUT1
VCOM OUT2
REFL OUT
REFL
APPLICATIONS
D REPLACES RESISTOR-BASED GAMMA
SOLUTIONS
D TFT-LCD REFERENCE DRIVERS
D DYNAMIC GAMMA CONTROL
DESCRIPTION
The BUF20820 is a programmable voltage reference
generator designed for gamma correction in TFT-LCD
panels. It provides 18 programmable outputs for gamma
correction and two channels for VCOM adjustment, each
with 10-bit resolution. It offers on-chip One-Time
Programmable (OTP) memory that allows the user to store
the gamma voltages on-chip. This eliminates the need for
an external EEPROM.
This programmability replaces the traditional, time-
consuming process of changing resistor values to optimize
the various gamma voltages and allows designers to
determine the correct gamma voltages for a panel very
quickly. Required voltage changes can also be easily
implemented without hardware changes.
The BUF20820 uses TI’s latest, small-geometry analog
CMOS process, which makes it a very competitive choice
for full production, not just evaluation.
Programming of each output occurs through an industry-
standard, two-wire serial interface. Unlike existing
programmable buffers, the BUF20820 offers a high-speed
mode that allows clock speeds up to 3.4MHz.
For lower or higher channel count, please contact your
local sales or marketing representative.
The BUF20820 is available in an HTSSOP-38
PowerPAD package. It is specified from −40°C to +85°C.
BUF20820 RELATED PRODUCTS
FEATURES
18-Channel Programmable, Two VCOM
12-Channel Programmable Buffer, 10-Bit
Programmable VCOM with Memory
10-Channel Gamma Correction Buffer, Int VCOM,
18V Operating Supply Voltage
High-Speed VCOM, 1 and 2 Channels
Complete LCD DC/DC Solution
PRODUCT
BUF20800
BUF12800
BUF01900
BUF11704
SN10501
TPS651xx
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2005−2006, Texas Instruments Incorporated
www.ti.com
1 page  
BUF20820
www.ti.com
SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
ANALOG SUPPLY CURRENT vs TEMPERATURE
10
VS = 18V
8
VS = 10V
6
4
2
0
−40 −20
0
20 40 60 80 100
Temperature (_ C)
Figure 1
DIGITAL SUPPLY CURRENT vs TEMPERATURE
30
VS = 10V
25
VSD = 5V
20
15
VSD = 3.3V
10
5
0
−40
−20
0
20 40 60 80 100
Temperature (_ C)
Figure 2
FULL−SCALE OUTPUT SWING
REFH = 17V
REFL = 1V
Code 3FF →000
Code 000 →3FF
Time (1µs/div)
Figure 3
OUTPUT VOLTAGE vs OUTPUT CURRENT
18
17
16 OUT10−18 (sourcing), Code = 3FFh
15
VREFL = 0.2V, VREFH = 17V
RLOAD Connected to GND
3 OUT1−9, VCOM1−2 (sinking)
Code = 000h
2 VREFL = 1V, VREFH = 17.8V
RLOAD Connected to 18V
1
OUT1−9, VCOM1−2 (sourcing)
Code = 3FFh
VREFL = 1V, VREFH = 17.8V
RLOAD Connected to GND
OUT10−18 (sinking), Code = 000h
VREFL = 0.2V, VREFH = 17V
RLOAD Connected to 18V
0
0 10 20 30 40 50 60 70 80 90 100
Output Current (mA)
Figure 4
INTEGRAL NONLINEARITY ERROR vs INPUT CODE
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
0
200 400 600 800 1000
Input Code
Figure 5
DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
0
200 400 600 800 1000
Input Code
Figure 6
5
5 Page 
BUF20820
www.ti.com
Write: OTP Memory for the DAC Register
The BUF20820 is able to write to the OTP memory of a
single DAC, or multiple DACs in a single communication
transaction. DAC addresses begin with 00000 (which
corresponds to DAC_1) through 10011 (which corre-
sponds to VCOM OUT2).
When programming the OTP memory, the analog supply
voltage must be between 8.5V and 18V.
Write commands are performed by setting the read/write
bit LOW.
To write to a single OTP register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D5 must be set to
0. Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10100 are valid and will be
acknowledged. See Table 3 for DAC addresses.
4. Send two bytes of data for the OTP register of the
specified DAC. Begin by sending the most significant
byte first (bits D15−D8, of which only bits D9 and D8
are data bits, and bits D15−D14 must be 01), followed
by the least significant byte (bits D7−D0). For address
10100, only D0 has meaning. This bit is the write
disable bit. The register is updated after receiving the
second byte.
5. Send a STOP condition on the bus.
The BUF20820 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified OTP
register will not be updated. Writing an OTP register will
also update the DAC register and output voltage.
SBOS330C − DECEMBER 2005 − REVISED OCTOBER 2006
To write to multiple OTP registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the
OTP register of the first DAC, or send the address byte
for whichever DAC will be the first in the sequence to
be updated. The BUF20820 will begin with the OTP
register of this DAC and step through subsequent
registers in sequential order.
4. Send the bytes of data; begin by sending the most
significant byte (bits D15−D8, of which only bits D9
and D8 have meaning, and bits D15−D14 must be 01),
followed by the least significant byte (bits D7−D0). The
first two bytes are for the OTP register of the DAC
addressed in step 3 above. This OTP register is
automatically updated after receiving the second byte.
The next two bytes are for the OTP register of the
following DAC (bits D15−D14 must again be 01). That
DAC OTP register is updated after receiving the fourth
byte. This process continues until the registers of all
following DAC OTP registers have been updated. The
last address, 10100, is the address of the write disable
bit and cannot be accessed using this method. It must
be written using the write to a single OTP register
procedure.
5. Send a STOP condition on the bus.
The BUF20820 will acknowledge each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DAC registers that have received both bytes of
data will be programmed.
OTP WRITE DISABLE
Writing a ‘1’ in bit D0 of register 10100 disables all future
writes. The state of this bit can be accessed the same as
any other data bit. It is important to set this bit to 1 after the
OTP registers have been programmed to prevent
accidental changes to the OTP registers. Until bit D0 of
register 10100 is set to 1, any OTP register bit can be
changed from 0 to 1; however, once a bit is set to a 1, it
cannot be set back to 0.
11
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet BUF20820.PDF ] | |
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