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PDF CY28349B Data sheet ( Hoja de datos )
| Número de pieza | CY28349B | |
| Descripción | FTG | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY28349B (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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CY28349B
FTG for Intel® Pentium® 4 CPU and Chipsets
Features
• Compatible to Intel® CK-Titan and CK-408 Clock
Synthesizer/driver specifications
• System frequency synthesizer for Intel Brookdale 845
and Brookdale – G Pentium® 4 chipsets
• Programmable clock output frequency with less than
1-MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to hardware-selected or software-
programmed clock frequency when w timer time-out
• Fixed 3V66 and PCI output frequency mode.
• Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength support
• Programmable output skew support
• Power management control inputs
• Available in 48-pin SSOP
CPU 3V66 PCI REF 48M 24_48M
x 3 x 4 x 10 x 2 x 1 x 1
Block Diagram
X1
X2
*FS0:4
VTT_PWRGD#
*MULTSEL0:1
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XTAL
OSC
PLL Ref Freq
PLL 1
Divider
Network
PWR_DWN#
PLL2
SDATA
SCLK
SMBus
Logic
2
VDD_REF
REF0:1
Pin Configuration [1]
*MULTSEL1/REF1
VDD_CPU
CPU0:1, CPU0:1#,
VDD_REF
CPU_ITP, CPU_ITP#
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
VDD_3V66
*FS4/PCI0
3V66_0:2
PCI1
PCI2
VDD_PCI
PCI_F0:2
GND_PCI
PCI3
PCI4
PCI0:6
VDD_48MHz
PCI5
PCI6
3V66_3/48MHz_1
VDD_PCI
VDD_48MHz
VTT_PWRGD#
48MHz_0
RST#
GND_48MHz
24_48MHz
*FS0/48MHz_0
*FS1/24_48MHz
VDD_48MHz
RST#
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
SSOP-48
REF0/MULTSEL0*
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWR_DWN#
CPU0
CPU0#
VDD_CPU
CPU1
CPU1#
GND_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3/48MHz_1
SCLK
SDATA
Note:
1. Signals marked with ‘*’ and “^” have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07454 Rev. *A
Revised December 17, 2002
1 page  
CY28349B
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or
disabled.
The register associated with the Serial Data Interface
initializes to its default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
The clock driver serial protocol accepts Byte Write, byte read,
Block Write and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code, as
described in Table 1.
The Block Write and Block Read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol.
Table 1. Command Code Definition
The slave receiver address is 11010010 (D2h).
Bit Descriptions
7
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
6:0
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations,
these bits should be ‘0000000’.
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit Description
1 Start
2:8 Slave address – 7 bits
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9
Write
10 Acknowledge from slave
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
19 Acknowledge from slave
20:27 Byte Count – 8 bits
28 Acknowledge from slave
29:36 Data byte 0 – 8 bits
37 Acknowledge from slave
38:45 Data byte 1 – 8 bits
46 Acknowledge from slave
... Data Byte N/Slave Acknowledge...
... Data Byte N – 8 bits
... Acknowledge from slave
... Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
...
...
...
...
Block Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit Description
1 Start
2:8 Slave address – 7 bits
Byte Read Protocol
Bit Description
1 Start
2:8 Slave address – 7 bits
Document #: 38-07454 Rev. *A
Page 5 of 22
5 Page 
Data Byte 12
Bit
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
–
–
–
–
–
–
Data Byte 13
Name
ROCV_FREQ_M6
ROCV_FREQ_M5
ROCV_FREQ_M4
ROCV_FREQ_M3
ROCV_FREQ_M2
ROCV_FREQ_M1
ROCV_FREQ_M0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
–
–
–
–
–
–
–
Data Byte 14
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Bit
Bit 7
Pin#
–
Name
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
CPU_FSEL_N0
Name
Pro_Freq_EN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
– CPU_FSEL_M6
– CPU_FSEL_M5
– CPU_FSEL_M4
– CPU_FSEL_M3
– CPU_FSEL_M2
– CPU_FSEL_M1
– CPU_FSEL_M0
Data Byte 15
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
–
–
–
–
–
–
–
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Vendor Test Mode
Vendor Test Mode
Document #: 38-07454 Rev. *A
CY28349B
Pin Description
If ROCV_FREQ_SEL is set, the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be
used to determine the recovery CPU output
frequency.when a Watchdog Timer time-out occurs.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When FS_Override
bit is cleared, the same frequency ratio stated in the
Latched FS[4:0] register will be used. When it is set, the
frequency ratio stated in the SEL[4:0] register will be used.
Power On
Default
0
0
0
0
0
0
0
Pin Description
If Prog_Freq_EN is set, the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used
to determine the CPU output frequency. The new
frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When it is cleared,
the same frequency ratio stated in the Latched FS[4:0]
register will be used. When it is set, the frequency ratio
stated in the SEL[4:0] register will be used.
Power On
Default
0
0
0
0
0
0
0
0
Pin Description
Programmable output frequencies enabled
0 = Disabled
1 = Enabled
If Prog_Freq_EN is set, the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used
to determine the CPU output frequency. The new
frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When it is cleared,
the same frequency ratio stated in the Latched FS[4:0]
register will be used. When it is set, the frequency ratio
stated in the SEL[4:0] register will be used.
Power On
Default
0
0
0
0
0
0
0
0
Pin Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved. Write with “1”
Reserved. Write with “1”
Power On
Default
0
0
0
0
0
0
1
1
Page 11 of 22
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CY28349B.PDF ] | |
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