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PDF AS8F128K32 Data sheet ( Hoja de datos )
| Número de pieza | AS8F128K32 | |
| Descripción | 128K x 32 FLASH FLASH MEMORY ARRAY | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
FLASH
AS8F128K32
128K x 32 FLASH
FLASH MEMORY ARRAY
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
68 Lead CQFP (Q & Q1)
SPECIFICATIONS
• SMD 5962-94716
• MIL-STD-883
FEATURES
• Fast Access Times: 60, 70, 90, 120 and 150ns
• Operation with single 5V (±10%)
• Compatible with JEDEC EEPROM command set
• Any Combination of Sectors can be Erased
• Supports Full Chip Erase
• Embedded Erase and Program Algorithms
• TTL Compatible Inputs and CMOS Outputs
• Hardware Data Protection
• Data\ Polling and Toggle Bits
• Low Power consumption
• Individual Byte Read/ Write Control
• 10,000 Program/Erase Cycles
OPTIONSwww.DataSheet4U.com
• Timing
60ns
70ns
90ns
120ns
150ns
MARKINGS
-60
-70
-90
-120
-150
• Package
Ceramic Quad Flat pack
Ceramic Quad Flat pack
Q No. 703
Q1
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8F128K32 is a 4 Megabit
CMOS FLASH Memory Module organized as 128K x 32 bits. The
AS8F128K32 achieves high speed access (60 to 150 ns), low power
consumption and high reliability by employing advanced CMOS
memory technology.
The device is designed to be programmed in-system with the
standard system 5.0V VCC supply. A 12.0V VPP is not required for
program or erase operation. The device can also be programmed or
erased in standard EPROM programmers. To eliminate bus
contention the device has seperate chip enbaled (CEx\), write enable
(WEx\) and output enable (OE) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC
single-power-supply Flash standard. Commands are written to the
command register using standard microprocessor write timings.
Register contents serve as input to an internal state machine that
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
controls the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program command
sequence. This invokes the Embedded Program algorithm—an internal
algorithm that automatically times the program pulse widths and
verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This invokes the Embedded Erase algorithm—an internal algorithm
that automatically preprograms the array (if it is not already
programmed) before executing the erase operation. During erase, the
device automatically times the erase pulse widths and verifies proper
cell margin.
The host system can detect whether a program or erase operation
is complete by reading the I/O7 (Data\ Polling) and I/O6 (toggle)
status bits. After a program or erase cycle has been completed, the
device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased
and reprogrammed without affecting the data contents of other
sectors. The device is erased when shipped from the factory.
The hardware data protection measures include a low VCC
detector automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both
program and erase operations in any combination of the sectors of
memory, and is implemented using standard EPROM programmers.
The system can place the device into the standby mode. Power
consumption is greatly reduced in this mode.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM programming
mechanism of hot electron injection.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
FLASH
AS8F128K32
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and erase
operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected. It is
possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up and
power-down. The command register and all internal program/
erase circuits are disabled, and the device resets. Subsequent
writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE\, CEx\ or
WEx\ do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE\ = VIL,
CEx\ = VIH or WEx\ = VIH. To initiate a write cycle, CEx\ and
WEx\ must be a logical zero while OE\ is a logical one.
Power-Up Write Inhibit
If WEx\ = CEx\ = VIL and OE\ = VIH during power up, the device
does not accept commands on the rising edge of WEx\. The
internal state machine is automatical ly reset to reading array
data on power-up.
TABLE 3: Autoselect Codes (High Voltage Method)
DESCRIPTION
Manufacturer ID: AMD
A16 A13
CEx\ OE\ WEx\ to to
A14 A10
L L H XX
A9
A8 to
A7
A6
A5
to
A2
A1
A0
VID X L X L L
I/O0 to I/O7
I/O8 to I/O15
I/O16 to I/O23
I/O24 to I/O31
01h
Device ID: AM29F010B
L L H X X VID X L X L H
20h
01h (protected)
L L H SA X VID X L X H L
00h
Sector Protection Verification
(unprotected)
LEGEND:
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
FLASH
AS8F128K32
I/O5: Exceeded Timing Limits
I/O5* indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5* produces a “1.” This is a failure condition
that indicates the program or erase cycle was not successfully
completed.
The I/O5* failure condition may appear if the system tries
to program a “1” to a location that is previously programmed to
“0.” Only an erase operation can change a “0” back to a “1.”
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, I/O5* produces a
“1.” Under both these conditions, the system must issue the
reset command to return the device to reading array data.
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read I/O3* to determine whether or not an erase
operation has begun. (The sector erase timer does not apply to
the chip erase command.) If additional sectors are selected for
erasure, the entire timeout also applies after each additional
sector erase command. When the time-out is complete, I/O3*
switches from “0” to “1.” The system may ignore I/O3* if the
system can guarantee that the time between additional sector
erase commands will always be less than 50 ms. See also the
“Sector Erase Command Sequence” section.
After the sector erase command sequence is written, the
system should read the status on I/O7* (Data\ Polling) or I/O6
(Toggle Bit I) to ensure the device has accepted the command
sequence, and then read I/O3. If I/O3 is “1”, the internally
controlled erase cycle has begun; all further commands are
ignored until the erase operation is complete. If I/O3 is “0”, the
device will accept additional sector erase commands. To
ensure the command has been accepted, the system software
should check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 5 shows the outputs for I/O3.
TABLE 5: Write Operation Status
OPERATION
I/O71,*
I/O6*
I/O52,*
I/O3*
Embedded Program Algorithm
I/O7\ Toggle
0
N/A
Embedded Erase Algorithm
0 Toggle 0
1
NOTES: *applies to every 8th byte
1. I/O7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “I/O5: Exceeded
Timing Limits” for more information.
ABSOLUTE MAXIMUM RATINGS*
Voltage with respect to Ground, VCC1.........................-2.0V to +7.0V
Voltage with respect to Ground, A92..........................-2.0V to +14V
Voltage with respect to Ground, All other pins1......-2.0V to +7.0V
Short-circuit output current.....................................................200mA
Ambient Temperature with power Applied...............-55°C to 125°C
Storage temperature range..........................................-65°C to 150°C
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
NOTES:
1. Minimum DC voltage on input or I/O pin is –0.5 V. During voltage transitions, inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 5. Maximum DC on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods
up to 20 ns. See Figure 6.
2. Minimum DC input voltage on A9 pin is –0.5V. During voltage transitions, A9 pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 5. Maximum DC input voltage on A9 is +12.5 V which may overshoot to 14V for periods up to 20 ns.
3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
FIGURE 5: Maximum Negative Overshoot FIGURE 6: Maximum Positive Overshoot
AS8F128K32
Rev. 2.0 5/03
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AS8F128K32.PDF ] | |
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