PDF AS5SS256K18 Data sheet ( Hoja de datos )

Número de pieza	AS5SS256K18
Descripción	256K x 18 SSRAM Synchronous Burst SRAM
Fabricantes	Austin Semiconductor
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SSRAM AS5SS256K18 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through FEATURES • Fast access times: 8, 10, and 15ns • Fast clock speed: 113, 100, and 66 MHz • Fast clock and OE\ access times • Single +3.3V +0.3V/-0.165V power supply (VDD) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE WRTIE control and GLOBAL WRITE • Three chip enables for simple depth expansion and address pipelining • Clock-controlled and registered addresses, data I/Os and control signals • Interally self-timed WRITE cycle • Burst control pin (interleaved or linear burst) • Automatic power-down • Low capacitive bus loading • Operating Temperature Ranges: www.DataSheet4U.com - Military -55oC to +125oC - Industrial -40oC to +85oC OPTIONS MARKING • Timing 7.5ns/8ns/113 MHz 8.5ns/10ns/100 MHz 10ns/15ns/66 MHz • Packages 100-pin TQFP • Operating Temperature Ranges: - Military -55oC to +125oC - Industrial -45oC to +85oC -8* -9 -10 DQ No. 1001 IT XT available as IT only. For more products and information please visit our web site at www.austinsemiconductor.com GENERAL DESCRIPTION The Austin Semiconductor, Inc. Synchronous Burst SRAM family employs high-speed, low power CMOS designs that are fabricated us- ing an advanced CMOS process. ASI’s 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\, PIN ASSIGNMENT (Top View) 100-pin TQFP NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 2 80 3 79 4 78 5 77 6 76 7 75 8 74 9 73 10 72 11 71 12 70 13 69 14 68 15 67 16 66 17 65 18 64 19 63 20 62 21 61 22 60 23 59 24 58 25 57 26 56 27 55 28 54 29 53 30 52 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities. CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\). Asynchronous inputs include the output enable (OE\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\, is also asynchronous. WRITE cycles can be from one to two bytes wide, as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\) or address status controller (ADSC\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst ad- vance input (ADV\). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on this x18 device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins and DQPb. GW\ LOW causes all bytes to be written. Parity bits are available on this device. ASI’s 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. The de- vice is ideally suited for 486, Pentium®, and PowerPC systems and those systems that benefit from a wide synchronous data bus. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 1 page Austin Semiconductor, Inc. SSRAM AS5SS256K18 ABSOLUTE MAXIMUM RATINGS Voltage on VDD Supply Relative to VSS............-0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS.........-0.5V to +4.6V Storage Temperature (plastic) .....................-55°C to +125°C Max Junction Temperature*.......................................+150°C Short Circuit Output Current..........…...........................100mA Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC and -40oC<TA<+85oC; VDD = +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS (0V<VIN<VDD) Output(s) disabled; 0V<VIN<VDD IOH = -4.0mA IOL = 8.0 mA SYMBOL VIH VIL ILI ILO VOH VOL VDD VDDQ MIN 2.0 -0.3 -2 -2 2.4 -- 3.135 3.135 MAX VDD +0.3 0.8 2 2 -- 0.5 3.6 3.6 UNITS V V µΑ µΑ V V V V NOTES 1, 2 1, 2 3 1, 4 1, 4 1 1, 5 CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS TA = 25°C; f = 1MHz; VDD = 3.3V SYM CI CO CA CCK MAX 4 5 3.5 3.5 UNITS pF pF pF pF NOTES 6 6 6 6 THERMAL RESISTANCE DESCRIPTION CONDITIONS Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 SYM θJA θJC TYP 46 2.8 UNITS °C/W NOTES 6 °C/W 6 NOTES: 1. All voltages referenced to VSS (GND) 2. Overshoot: VIH < +4.6V for t < tKC/2 for I < 20mA Undershoot: VIL > -0.7V for t < tKC/2 for I < 20mA Power-up: V < +3.6V and V <3.135V for t < 200ms IH DD 3. MODE pin has an internal pull-up, and input leakage = ±10µA. 4. The load used for V , V testing is shown in Figure 2 for 3.3V I/O. AC load current is higher then the stated DC values. OH OL 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only. 6. This parameter is sampled. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 5 Page Austin Semiconductor, Inc. SSRAM AS5SS256K18 t READ/WRITE TIMING6 KC tKL CLK ADSP\ 111111222222333333444444555555 tADSS 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 t1111111K2222222H3333333444444455555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111112222222233333333444444445555555566666666 111111112222222233333333444444445555555566666666 111111112222222233333333444444445555555566666666 111111112222222233333333444444445555555566666666 111111112222222233333333444444445555555566666666 111111112222222233333333444444445555555566666666 ADSC\ 111111222222333333444444555555 111111222222333333444444555555666666 tA11111112222222D3333333S4444444H55555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 111111222222333333444444555555666666 11111112222222333333344444445555555 111111122222223333333444444455555556666666 ADDRESS A1 A2 A3 A4 A5 A6111111222222333333 tAS 111111222222333333444444111111555555222222666666333333777777444444888888555555666666777777888888 111111222222333333444444555555111111666666222222777777333333888888444444555555666666777777888888 111111222222333333444444111111555555222222666666333333777777444444888888555555666666777777888888999999000000111111222222333333444444555555666666777777888888999999000000111111222222333333444444555555666666777777888888999999000000111111222222111111222222333333111111444444555555666666777777888888 111111222222333333 BWE\, GW\ BWa\ - BWb\ CE\ (Note 2) t 111111222222333333444444555555111111122222223333333444444455555556666666A77777778888888H9911111199999222222333333444444555555 t 111111222222333333444444555555666666777777888888999999000000111111222222333333444444555555 WS 111111222222333333444444555555666666777777888888999999000000111111222222333333 111111222222333333444444555555666666 1111111122222222333333334444444455555555t66666666CES 1111111222222233333334444444555555511111112222222333333344444445555555666666677777778888888991111111999992222222333333344444445555555 t 11111122222233333344444455555511111112222222333333344444445555555W66666667777777H888888899111111999991222222233333334444444 1111111222222233333334444444555555511111112222222333333344444445555555666666677777778888888999999900000001111111222222233333334444444555555566666667777777888888899999990000000111111122222223333333444444455555556666666777777788888889999999000000011111112222222111111122222223333333444444455555556666666777777788888881111111222222233333334444444 111111112222222233333333444444445555555566666666 1111111122222222333333334444444455555555 111111112222222233333333444444445555555566666666 111111112222222233333333444444445555555566666666 ADV\ 111111222222333333444444555555666666777777888888999999000000111111222222333333444444555555666666777777888888t999999C000000E111111222222H333333444444555555666666777777888888999999000000111111222222111111222222333333444444555555666666777777888888999999000000111111111111222222223333332222111111444444222222555555666666 111111222222333333444444555555666666777777888888999999000000111111222222333333444444555555666666777777888888 111111222222333333444444555555666666777777888888999999000000111111222222333333444444555555666666777777 111111122222223333333444444455555556666666 111111122222223333333444444455555556666666 OE\ tDS tDH D Q High-Z 1111222233334444 Q(A1) 111122223333 tOEHZ Q(A2) D(A3) tOELZ 1111tKQQ(A4) 111222(NQO(AT4+E1)1)111222 Q(A4+2) 111222 Q(A4+3) D(A5) D(A6) Back-to-Back READS (NOTE 5) SINGLE WRITE READ/WRITE PARAMETERS -8 -9 -10 SYM MIN MAX MIN MAX MIN MAX UNITS tKC 8.8 10 15 ns tKF 113 100 66 MHz tKH 2.5 3.0 4.0 ns tKL 2.5 3.0 4.0 ns tKQ 7.5 8.5 10 ns tOELZ 0 0 0 ns tOEHZ 3.5 4.2 5.0 ns tAS 1.5 1.8 2.0 ns tADSS 1.5 1.8 2.0 ns BURST READ Back-to-Back WRITEs 111112222233333444445555566666Don’t Care 1111122222333334444455555 Undefined SYM tWS tDS tCES tAH tADSH tWH tDH tCEH -8 -9 -10 MIN MAX MIN MAX MIN MAX UNITS 1.5 1.8 2.0 ns 1.5 1.8 2.0 ns 1.5 1.8 2.0 ns 0.5 0.5 0.5 ns 0.5 0.5 0.5 ns 0.5 0.5 0.5 ns 0.5 0.5 0.5 ns 0.5 0.5 0.5 ns NOTE: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4. 2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP\, ADSC\, or ADV\ cycle is performed. 4. GW\ is HIGH. 5. Back-to-back READs may be controlled by either ADSP\ or ADSC\. 6. Timing is shown assuming that the device was not enabled before entering into this sequence. AS5SS256K18 Rev. 2.0 12/00 11 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 Page

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