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PDF AS5SS128K36 Data sheet ( Hoja de datos )
| Número de pieza | AS5SS128K36 | |
| Descripción | 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
SRAM
AS5SS128K36
128K x 36 SSRAM
SYNCHRONOUS ZBL SRAM
FLOW-THRU OUTPUT
FEATURES
• High frequency and 100% bus utilization
• Fast cycle times: 11ns & 12ns
• Single +3.3V +5% power supply (VDD)
• Advanced control logic for minimum control signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W\ (READ/WRITE) control pin
• CKE\ pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data I/Os and
control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to eliminate the
need to control OE\
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
www.DataSheet4U.com • Burst feature (optional)
• Pin/function compatibility with 2Mb, 8Mb, and 16Mb ZBL
SRAM
• Automatic power-down
OPTIONS
• Timing (Access/Cycle/MHz)
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
MARKING
-11
-12
• Packages
100-pin TQFP
DQ No. 1001
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
For more products and information
please visit our web site at
www.austinsemiconductor.com
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. Zero Bus Latency SRAM
family employs high-speed, low-power CMOS designs using an ad-
vanced CMOS process.
ASI’s 4Mb ZBL SRAMs integrate a 128K x 36 SRAM core
with advanced synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMS are optimized for 100 percent bus utilization,
eliminating any turnaround cycles for READ to WRITE, or WRITE
to READ, transitions. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input (CLK). The
synchronous inputs include all addresses, all data inputs, chip enable
(CE\), two additional chip enables for easy depth expansion (CE2,
CE2\), cycle start input (ADV/LD\), synchronous clock enable (CKE\),
byte write enables (BWa\, BWb\, BWc\, and BWd\) and read/write (R/
W\).
Asynchronous inputs include the output enable (OE\, which
may be tied LOW for control signal minimization), clock (CLK) and
snooze enable (ZZ, which may be tied LOW if unused). There is also
a burst mode pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left unconnected if
burst is unused. The flow-through data-out (Q) is enabled by OE\.
WRITE cycles can be from one to four bytes wide as controlled by the
write control inputs.
All READ, WRITE and DESELECT cycles are initiated by
the ADV/LD\ input. Subsequent burst addresses can be internally
generated as controlled by the burst advance pin (ADV/LD\). Use of
burst mode is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.
To allow for continuous, 100 percent use of the data bus,
the flow-through ZBL SRAM uses a LATE WRITE cycle. For ex-
ample, if a WRITE cycle begins in clock cycle one, the address is
present on rising edge one. BYTE WRITEs need to be asserted on the
same cycle as the address. The write data associated with the address
is required one cycle later, or on the rising edge of clock cycle two.
Address and write control are registered on-chip to simplify
WRITE cycles. This allows self-timed WRITE cycles. Individual
byte enables allow individual bytes to be written. During a BYTE
WRITE cycle, BWa\ controls DQa pins; BWb\ controls DQb pins;
BWc\ controls DQc pins; and BWd\ controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e., when ADV/LD\ is
LOW. Parity/ECC bits are available on this device.
Austin’s 4Mb ZBL SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are LVTTL-compatible.
The device is ideally suited for systems requiring high bandwidth and
zero bus turnaround delays.
AS5SS128K36
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
SRAM
AS5SS128K36
FUNCTIONAL BLOCK DIAGRAM
SA0, SA1, SA
17
CLK
CKE\
MODE
K
CE
ADDRESS
REGISTER
17 15 17
SA1
SA0
D1
D0
ADV/LD\
K
BURST
LOGIC
SA1'
Q1 SA0'
Q0
17
WRITE ADDRESS
REGISTER
17
ADV/LD\
BWa\
BWb\
BWc\
BWd\
R/W\
OE\
CE\
CE2
CE2\
WRITE REGISTRY AND
DATA COHERENCY
CONTROL LOGIC
READ
LOGIC
O
S
E
N
D
A
T
A
U
T
P
U
T
128K X 9 X 4
S
WRITE
DRIVERS
MEMORY
ARRAY
E
S
T
B DQs
A
M
P
S
E
E
R
I
N
G
U
F
F
E
R
S
E
INPUT E
REGISTER
NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed
information.
AS5SS128K36
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels
Input slew rate
Input timing reference levels
Output reference levels
Output load
Vss to 3.3V
1 ns
1.5V
1.5V
See Figures 1 and 2
SRAM
AS5SS128K36
OUTPUT LOADS
3.3v
Q
Z0=50Ω
50Ω
VT =1.5V
Q
351Ω
317Ω
5 pF
Fig. 1 OUTPUT LOAD EQUIVALENT
Fig. 2 OUTPUT LOAD EQUIVALENT
LOAD DERATING CURVES
The ASI 128K x 36 ZBL SRAM timing is dependent upon
the capacitive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
AS5SS128K36
Rev. 2.0 12/00
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
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