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PDF AS5LC512K8 Data sheet ( Hoja de datos )
| Número de pieza | AS5LC512K8 | |
| Descripción | 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
512K x 8 SRAM
3.3 VOLT HIGH SPEED SRAM with
CENTER POWER PINOUT
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883 for Ceramic
•Extended Temperature Plastic (COTS)
SRAM
AS5LC512K8
PIN ASSIGNMENT
(Top View)
36-Pin PSOJ (DJ)
36-Pin CLCC (EC)
FEATURES
• Ultra High Speed Asynchronous Operation
• Fully Static, No Clocks
• Multiple center power and ground pins for improved
noise immunity
• Easy memory expansion with CE\ and OE\
options
• All inputs and outputs are TTL-compatible
• Single +3.3V Power Supply +/- 0.3%
• Data Retention Functionality Testing
• Cost Efficient Plastic Packaging
•www.DataSheet4U.com Extended Testing Over -55ºC to +125ºC for plastics
OPTIONS
• Timing
12ns access
15ns access
20ns access
MARKING
-12
-15
-20
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
• Package(s)
Ceramic Flatpack
Plastic SOJ (400 mils wide)
Ceramic LCC
F No. 307
DJ
EC No. 210
• 2V data retention/low power
L
For more products and information
please visit our web site at
www.austinsemiconductor.com
36-Pin Flat Pack (F)
GENERAL DESCRIPTION
The AS5LC512K8 is a 3.3V high speed SRAM. It offers
flexibility in high-speed memory applications, with chip enable (CE\)
and output enable (OE\) capabilities. These features can place the
outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
As a option, the device can be supplied offering a reduced power
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5LC512K8DJ offers the convenience and reliability of the
AS5LC512K8 SRAM and has the cost advantage of a plastic
encapsulation.
AS5LC512K8
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................................... Vss to 3.0V
Input rise and fall times ......................................................... 3ns
Input timing reference levels ............................................... 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1 and 2
RL = 50Ω
Q
ZO=50Ω
30 pF
VL = 1.5V
Q
353Ω
SRAM
AS5LC512K8
3.3V
319Ω
5 pF
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. All voltages referenced to V (GND).
SS
2. ICC limit shown is for absolute worst case switching of
ADDR, ADDR\, ADDR, etc.
3. I is dependent on output loading and cycle rates.
CC
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Output enable (OE\) is inactive (HIGH).
14. Output enable (OE\) is active (LOW).
15. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
Vcc for Retention Data
CE\ > VCC -0.2V
VIN > VCC -0.2 or 0.2V
Data Retention Current
Vcc = 2.0V
Chip Deselect to Data
Operation Recovery Time
SYM
VDR
ICCDR
tCDR
tR
MIN MAX UNITS NOTES
2V
6.5
0
20
mA
ns
ms
4
4, 11
AS5LC512K8
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
SRAM
AS5LC512K8
MECHANICAL DEFINITIONS*
ASI Case #210 (Package Designator EC)
Pin 1 identifier area
1111111111222222222233333333334444444444555555555566666666667777777777
L2
1
R
P
A
D
36
L
eB
D1
E
A1
SYMBOL
A
A1
B
D
D1
E
e
L
L2
P
R
ASI SPECIFICATIONS
MIN MAX
0.080
0.100
0.054
0.066
0.022
0.028
0.910
0.930
0.840
0.860
0.445
0.460
0.050 BSC
0.100 TYP
0.115
0.135
--- 0.006
0.009 TYP
*All measurements are in inches.
AS5LC512K8
Rev. 1.0 7/02
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS5LC512K8.PDF ] | |
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