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PDF AS5C512K8 Data sheet ( Hoja de datos )
| Número de pieza | AS5C512K8 | |
| Descripción | 512K x 8 SRAM HIGH SPEED SRAM | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS5C512K8 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Austin Semiconductor, Inc.
SRAM
AS5C512K8
512K x 8 SRAM
HIGH SPEED SRAM with
REVOLUTIONARY PINOUT
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-95600
•SMD 5962-95613
•MIL-STD-883
FEATURES
• Ultra High Speed Asynchronous Operation
• Fully Static, No Clocks
• Multiple center power and ground pins for improved
noise immunity
• Easy memory expansion with CE\ and OE\
options
• All inputs and outputs are TTL-compatible
• Single +5V Power Supply +/- 10%
• Data Retention Functionality Testing (Contact Factory)
• Cost Efficient Plastic Packaging
• Extended Testing Over -55ºC to +125ºC for plastics
• Plastic 36 pin PSOJ is fully compatible with the
www.DataSheet4U.com
Ceramic 36 pin SOJ
• 3.3V Future Offering
OPTIONS
• Timing
15ns access
17ns access
20ns access
25ns access
35ns access
45ns access
MARKING
-15
-17
-20
-25
-35
-45
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
• Package(s)
Ceramic LCC
Ceramic Flatpack
Plastic SOJ
Ceramic SOJ
EC No. 210
F No. 307
DJ No. 903
ECJ No.503
• 2V data retention/low power
L (Consult Factory)
• Radiation Tolerant (EPI)
E
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
36-Pin SOJ (DJ & ECJ)
36-Pin CLCC (EC)
36-Pin Flat Pack (F)
GENERAL DESCRIPTION
The AS5C512K8 is a high speed SRAM. It offers flexibility in
high-speed memory applications, with chip enable (CE\) and output
enable (OE\) capabilities. These features can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
As a option, the device can be supplied offering a reduced power
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +5V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5C512K8DJ offers the convenience and reliability of the
AS5C512K8 SRAM and has the cost advantage of a durable plastic.
The AS5C512K8DJ is footprint compatible with 36 pin CSOJ
package of the SMD 5692-95600.
AS5C512K8
Rev. 4.5 7/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................................... Vss to 3.0V
Input rise and fall times ......................................................... 3ns
Input timing reference levels ............................................... 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1 and 2
SRAM
AS5C512K8
Q
167 ohms
1.73V
Q
167 ohms
1.73V
C=30pF
C=5pF
Fig. 1 Output Load
Equivalent
NOTES
1. All voltages referenced to VSS (GND).
2. -2V for pulse width < 20ns
3. ICC is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE.
8. WE\ is HIGH for READ cycle.
Fig. 2 Output Load
Equivalent
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Output enable (OE\) is inactive (HIGH).
14. Output enable (OE\) is active (LOW).
15. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM MIN MAX
Vcc for Retention Data
CE\ > VCC -0.2V
VIN > VCC -0.2 or 0.2V
VDR
2
Data Retention Current
Vcc = 2.0V ICCDR
4.5
Chip Deselect to Data
tCDR
0
Operation Recovery Time
tR 10
UNITS
V
mA
ns
ms
NOTES
4
4, 11
AS5C512K8
Rev. 4.5 7/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
SRAM
AS5C512K8
MECHANICAL DEFINITIONS*
ASI Case #503 (Package Designator ECJ)
SMD 5962-95600, Case Outline M
P
A
L2
1
L
TYP
36
e
D1
b
D A2
E2
A1
E
SYMBOL
A
A1
A2
b
D
D1
E
E2
e
L
L2
P
*All measurements are in inches.
AS5C512K8
Rev. 4.5 7/01
SMD SPECIFICATIONS
MIN MAX
0.140
0.160
0.054
0.075
0.025
0.063
0.019
0.028
0.910
0.939
0.840
0.860
0.434
0.460
0.374
0.410
0.050 BSC
0.050
0.070
0.115
0.135
--- 0.004
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AS5C512K8.PDF ] | |
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