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PDF ISL6595 Data sheet ( Hoja de datos )
| Número de pieza | ISL6595 | |
| Descripción | Digital Multiphase Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
February 27, 2006
ISL6595
FN9192.0
Digital Multiphase Controller
The ISL6595 digital multiphase controller provides core
power for today’s high current microprocessors by driving up
to six synchronous-rectified buck-converter channels in
parallel. Interleaved timing of the channels results in a higher
ripple frequency, reducing input and output ripple. With up to
six phases, each capable of up to 2MHz operation, the
ISL6595 can be used to build DC/DC converters that provide
up to 200A with excellent efficiency, low ripple, and the
lowest component count.
The ISL6595 utilizes digital technology to implement all
control functions, providing the ultimate in flexibility and
stability. The ISL6595 incorporates an industry standard I2C
serial interface for control and monitoring. Through the serial
interface, the power supply designer can quickly optimize
designs and monitor parameters. The interface allows the
ISL6595 to provide digitized information for real time system
monitoring and control.
The ISL6595 provides superior loadline accuracy through
internal calibration that measures and corrects current sense
error sources upon startup. The ISL6595 has programmable
current sense temperature compensation that allows the
designer to tailor the response for best loadline accuracy
over temperature. Superior loadline accuracy reduces
component count and solution cost.
To further reduce component count the ISL6595
incorporates patented Active Transient Response (ATR)
technology, allowing the fastest response to transient events
for reduced output capacitance.
The flexibility of the ISL6595 allows the power supply
designer to implement a wide range of solutions. When used
with industry standard power train components, the ISL6595
provides the highest performance with lowest component
count and cost.
Ordering Information
PART
NUMBER
(Note)
PART TEMP PACKAGE
MARKING (°C)
(Pb-free)
PKG.
DWG #
ISL6595DRZ-T ISL6595DRZ 0 to 85 48 Ld 7x7 QFN L48.7x7P
Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Multiphase power conversion
- 1- to 6-phase operation
• 100kHz to 2MHz switching frequency
• Supports Intel® VR10.x and VR11.0 VID codes
• Supports AMD® 5-bit and 6-bit VID codes
• Internal high precision voltage reference
- ±10mV voltage setpoint accuracy
• Precision digital current sense calibration
• Precise digital current balancing with programmable
offsets for thermal balancing
• Digitally programmable loadline and loop compensation
• Differential voltage sense
• Digital temperature sensor compensation
• Active Transient Response (ATR) enables meeting
transient requirements with reduced output capacitance
• I2C interface for monitoring, control and configuration
• Internal non-volatile memory (NVM) to store custom
configurations
• Extensive fault detection capability with two user
configurable output fault pins (FAULT1, FAULT2)
- Input undervoltage
- Output under/overvoltage
- High side short
- Per phase and total output current
- Multiple internal and external temperature limits
- NVM configuration
- Calibration range and time-out
• Configurable latched fault or autonomous recovery
shutdown
• Single +3.3V supply operation
• Pb-free plus anneal available (RoHS compliant)
48 Ld QFN plastic package
Applications
• Core power regulation for Intel® and AMD® micro-
processors
• Intelligent point-of-load (POL) power regulation
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6595
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 4.25V
All Pins Except ISENx, VSENP,
VSENN and Ground . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 4.25V
All ISENx, VSENP, VSENN Pins . . . . . . . . . . . . . . . . -0.50V to 3.0V
All Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 0.50V
ESD (Per JEDEC JES22-A114-B, JESD22-C101A, JESD22-A115-A)
Human Body Model (100pF, 1.5kΩ) . . . . . . . . . . . . . . . . . . 3,000V
Charged Device Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1,000V
Vapor Phase (60s), TVAPOR . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15s), TIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +3.60V
Operating Case Temperature. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . 0°C to 85°C
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
31
3
Maximum Junction Temperature (Plastic Package) . . 0°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = +3.3V, TC = +25°C, unless otherwise specified
PARAMETER
SYMBOL
TEST CONDITIONS
VDD SUPPLY
Nominal Supply Current
RESET_N
IVDD
Input LOW Voltage
Input HIGH Voltage
Input Current, Input Voltage LOW
VIN = 0.0V
Input Current, Input Voltage HIGH
VIN = 3.5V
VID[7:0], OUTEN, LL0, LL1, VID_SEL (Note 3)
Input Low Voltage
Input High Voltage (Note 4)
Input Current, Input Voltage Low
VIN = 0.0V
Input Current, Input Voltage High
VIN = 3.5V
OUTEN INPUT
Input Threshold
Input Hysteresis
Input Bandwidth
VT_VR_EN
VH_VR_EN
SDA, SCL INPUTS
Input LOW Voltage
Input HIGH Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
Output LOW Voltage
VIL_S
VIH_S
IIL_S
IIH_S
VIN = 0.0V
VIN = 3.5V
MIN TYP MAX UNITS
- 100 140 mA
-0.3 - 0.5 V
2.8 - 3.6 V
-75 - -10 µA
- - - µA
-0.3 - 0.4 V
0.8 - 5.5 V
- -20 -30 µA
- 15 25 µA
0.8 0.85 0.9
V
- 100 - mV
- - 20 MHz
-0.3 - 0.8 V
2.4 - 5.5 V
-10 -
10 µA
-10 -
10 µA
- - 0.4 V
5 FN9192.0
February 27, 2006
5 Page 
ISL6595
algorithm compensates for variations in low-side FET
rDS(on), parasitic inductance and resistance by regulating to
a low voltage level, putting a known current load through
each phase individually and compensating for the current
sense gain and offset error, as well as changes in
temperature. Alternatively, default compensation values can
be used, or the compensation values can be computed
during system test and stored in memory. The external
current load needed to perform calibration can be
implemented with a precision resistor and N-channel FET.
The voltage across the resistor is sensed and the N-channel
FET gate voltage is adjusted through an internal op amp
loop to provide the desired precision current. The calibration
current level and the voltage level at which the calibration is
performed are both programmable.
After the soft-start ramp is completed, the regulator enters
the active regulation state and the VR_READY pin
transitions from “0” to “1”, indicating that the microprocessor
voltage is within ±10% of the target value.
VCC (500mV/DIV)
CAL_CUR_SEN
(100mV/DIV)
CAL_CUR_EN
(2V/DIV)
VR_READY
(2V/DIV)
4.0ms/DIV
FIGURE 3. SOFT-START/CALIBRATION SEQUENCE (3-PHASE)
Shutdown
The ISL6595 also performs a controlled shutdown response
to minimize any voltage undershoot. The shutdown state can
be entered from the soft-start or active regulation states
either through user intervention (de-asserting VR_EN or all
one’s VID), or through a detected fault such as over-
temperature or output overvoltage. During shutdown, the
PWM width is reduced at a steady programmable rate, and
then the power stage is three-stated once the pulse width
reaches 0.
After shutdown is complete, the controller re-enters the
inactive state after a fixed delay. This delay minimizes the
duty cycle associated with autonomous restarts if the fault
that caused the shutdown disappears once the output is
disabled. Alternatively, the fault can be configured so that it
is latched and clearing requires user intervention such as
toggling VR_EN, toggling RESET_N, or cycling power. If this
method is used, the user should ensure adequate delay is
provided to complete the shutdown prior to the start of a new
start-up. The delay may be as short as 2ms, although longer
delays are recommended to minimize the duty cycle in case
there is a fault which causes the start-up and shutdown cycle
to be repeated indefinitely.
Switching Frequency
Timing is provided by an on-chip, factory trimmed,
temperature compensated oscillator.
The ISL6595 operates with a fixed switching frequency (i.e.
the switching frequency is fixed independent of load) that is
configurable between 100kHz and 2MHz. A programmable
divider is used to generate the switching frequency, where
the frequency is given by:
Fsw = 156.25MHz/(2 x div_sel x Nph)
where Fsw is the switching frequency, 156.25MHz is the
nominal frequency of the timing reference oscillator, div_sel
is the programmable divider ratio between 6 and 127, and
Nph is the number of phases between 1 and 6.
Switching frequencies of less than 300kHz and greater than
1.5MHz are supported only for some number of phases
used.
Output Voltage Sensing and Voltage ADC
The ISL6595 is built around a high performance digital
feedback control loop that senses the differential voltage at
the load. This is used to generate the appropriate pulse
width modulated (PWM) waveforms to drive the power
stages and regulate the load voltage.
The differential sense voltage is digitized with a high speed,
high precision analog-to-digital converter (ADC). The on-
chip factory trimmed temperature compensated bandgap
voltage reference ensures the ADC accuracy is well within
the regulator setpoint accuracy requirements. The ADC is
sampled synchronously so that there are 2 ADC samples
per phase per switching cycle, at a frequency given by:
Fs = 156.25MHz/div_sel
The ADC also includes a post-filter which provides a null at
Fsw * (Nph/2), which is the ripple frequency. This ripple null
filter works in conjunction with an internal analog anti-alias
filter. The anti-alias filter is a single pole, 2MHz low pass
filter. The corner frequency can be lowered by adding series
resistors in the board.
Current Sensing and Current ADC
The ISL6595 provides for precise current monitoring in each
power stage, allowing for industry-leading loadline accuracy
for active voltage positioning (AVP). The current in each
power stage is sensed through one of three methods
supported by the ISL6595. These are single-ended rDS(on)
11 FN9192.0
February 27, 2006
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ISL6595.PDF ] | |
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