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PDF ISL6566 Data sheet ( Hoja de datos )
| Número de pieza | ISL6566 | |
| Descripción | Three-Phase Buck PWM Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
March 9, 2006
ISL6566
FN9178.4
Three-Phase Buck PWM Controller with
Integrated MOSFET Drivers for VRM9,
VRM10, and AMD Hammer Applications
The ISL6566 three-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. The integration of power MOSFET drivers
into the controller IC marks a departure from the separate
PWM controller and driver configuration of previous multi-
phase product families. By reducing the number of external
parts, this integration is optimized for a cost and space
saving power management solution.
Outstanding features of this controller IC include
programmable VID codes compatible with Intel VRM9,
VRM10, as well as AMD Hammer microprocessors. A unity
gain, differential amplifier is provided for remote voltage
sensing, compensating for any potential difference between
remote and local grounds. The output voltage can also be
positively or negatively offset through the use of a single
external resistor.
A unique feature of the ISL6566 is the combined use of both
DCR and rDS(ON) current sensing. Load line voltage
positioning (droop) and overcurrent protection are
accomplished through continuous inductor DCR current
sensing, while rDS(ON) current sensing is used for accurate
channel-current balance. Using both methods of current
sampling utilizes the best advantages of each technique.
Protection features of this controller IC include a set of
sophisticated overvoltage, undervoltage, and overcurrent
protection. Overvoltage results in the converter turning the
lower MOSFETs ON to clamp the rising output voltage and
protect the microprocessor. The overcurrent protection level
is set through a single external resistor. Furthermore, the
ISL6566 includes protection against an open circuit on the
remote sensing inputs. Combined, these features provide
advanced protection for the microprocessor and power
system.
Features
• Integrated Multi-Phase Power Conversion
- 1, 2, or 3-Phase Operation
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over Temperature
- Adjustable Reference-Voltage Offset
• Precision Channel Current Sharing
- Uses Loss-Less rDS(ON) Current Sampling
• Accurate Load Line Programming
- Uses Loss-Less Inductor DCR Current Sampling
• Variable Gate Drive Bias: 5V to 12V
• Microprocessor Voltage Identification Inputs
- Up to a 6-Bit DAC
- Selectable between Intel’s VRM9, VRM10, or AMD
Hammer DAC Codes
- Dynamic VID Technology
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Digital Soft-Start
• Selectable Operation Frequency up to 1.5MHz Per Phase
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6566 (QFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
VID1 1
VID0 2
VID12.5 3
VRM10 4
REF 5
OFS 6
VCC 7
COMP 8
FB 9
VDIFF 10
41
GND
30 BOOT1
29 PHASE1
28 PHASE2
27 UGATE2
26 BOOT2
25 ISEN2
24 PVCC2
23 LGATE2
22 PHASE3
21 BOOT3
11 12 13 14 15 16 17 18 19 20
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6566
Typical Application - ISL6566 with NTC Thermal Compensation
+5V
+12V
VDIFF
FB
VSEN
RGND
VCC
OFS
COMP PVCC1
BOOT1
UGATE1
PHASE1
ISEN1
LGATE1
FS
REF
PVCC2
VID4
VID3
VID2
VID1
VID0
VID12.5
VRM10
PGOOD
ISL6566
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PVCC3
GND
ENLL
IREF
OCSET
ICOMP
BOOT3
UGATE3
PHASE3
ISEN3
LGATE3
ISUM
+12V
+12V
+12V
PLACE IN CLOSE
PROXIMITY
NTC
LOAD
5 FN9178.4
March 9, 2006
5 Page 
ISL6566
Figures 22 and 23 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6566
is three. One switching cycle is defined as the time between
the internal PWM1 pulse termination signals. The pulse
termination signal is the internally generated clock signal
that triggers the falling edge of PWM1. The cycle time of the
pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low. The PWM1 transition signals the internal
channel-1 MOSFET driver to turn off the channel-1 upper
MOSFET and turn on the channel-1 synchronous MOSFET.
In the default channel configuration, the PWM2 pulse
terminates 1/3 of a cycle after the PWM1 pulse. The PWM3
pulse terminates 1/3 of a cycle after PWM2.
If PVCC3 is left open or connected to ground, two channel
operation is selected and the PWM2 pulse terminates 1/2 of
a cycle after the PWM1 pulse terminates. If both PVCC3 and
PVCC2 are left open or connected to ground, single channel
operation is selected.
Once a PWM pulse transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 3. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The internal MOSFET driver detects the
change in state of the PWM signal and turns off the
synchronous MOSFET and turns on the upper MOSFET.
The PWM signal will remain high until the pulse termination
signal marks the beginning of the next cycle by triggering the
PWM signal low.
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, In,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, IAVG, provides a measure of the total load-
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current-
balance method is illustrated in Figure 3, with error
correction for channel 1 represented. In the figure, the cycle
average current, IAVG, is compared with the channel 1
sample, I1, to create an error signal IER.
The filtered error signal modifies the pulse width
commanded by VCOMP to correct any unbalance and force
IER toward zero. The same method for error signal
correction is applied to each active channel.
VCOMP
+
-
FILTER f(s)
PWM1
+
-
SAWTOOTH SIGNAL
IER
IAVG
-
÷N
+
Σ
TO GATE
CONTROL
LOGIC
I3
I2
I1
NOTE: Channel 2 and 3 are optional.
FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Current Sampling
In order to realize proper current-balance, the currents in
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
transition low. During this time the current-sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, IL. This sensed current, ISEN, is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, tSW, after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the tSAMPLE, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel-current balance.
11 FN9178.4
March 9, 2006
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ISL6566.PDF ] | |
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