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PDF ISL95711 Data sheet ( Hoja de datos )
| Número de pieza | ISL95711 | |
| Descripción | 128 Taps I2C Serial Interface | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL95711
Digitally Controlled Potentiometer (XDCP™)
August 15, 2005
FN8241.2
Terminal Voltage ±3V or ±5V, 128 Taps I2C
Serial Interface
The Intersil ISL95711 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a I2C interface.
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. The wiper terminal can be connected to either end
of the resistor array or at any one of the Tap Positions in
between, providing 128 steps of resolution between RL and
RH. The “position” of the wiper is determined by the value
assigned to the volatile Wiper Register (WR). This register
has an associated non-volatile Initial Value Register (IVR).
The value stored in the IVR will be written into the WR at
power-up, allowing wiper position recall after power
interruption. The WR and the IVR can be directly written to
and read from using standard I2C interface protocol. The
device is available in either a 10kΩ or 50kΩ version.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
www.DataSheet4U.com
• Industrial and automotive control
• Parameter and bias adjustments
• Amplifier bias and control
Ordering Information
RESISTANCE
TEMP
PACKAGE
PART NUMBER OPTION (Ω) RANGE (°C) (Pb-Free)
ISL95711WIU10Z
(Notes 1& 2)
10K
-40 to +85 10-Ld MSOP
ISL95711UIU10Z
(Notes 1& 2)
50K
-40 to +85 10-Ld MSOP
NOTES:
1. Add “-T” suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Features
• Non-Volatile Solid-State Potentiometer
• I2C Serial Interface with Hardwire Slave Address Allows
Up to Four Devices
• DCP Terminal Voltage, from V- to VCC
• 128 Wiper Tap Points
- Wiper position can be stored in nonvolatile memory and
recalled on power-up
• 127 Resistive Elements
- Typical tempco ±50ppm/°C
- Ratiometric Tempco ±4ppm/°C
- End to end resistance range ±20%
• Low Power CMOS
- Standby current, 1µA
- Active current, 200µA max
- VCC = 3V to 5.5V
- V- = -3V to -5.5V
• High Reliability
- Endurance, 200,000 data changes per bit
- Register data retention, 50 years
• RTOTAL Values = 10kΩ, 50kΩ
• Package
- 10-lead MSOP
- Pb-Free plus anneal available (RoHS compliant)
Pinout
ISL95711
(10-LD MSOP)
TOP VIEW
SDA
V-
GND
A1
A0
1
2
3
4
5
10 SCL
9 VCC
8 RL
7 RW
6 RH
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL95711
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1)
tHIGH
tSU:STA
Clock HIGH time
START condition setup time
tHD:STA START condition hold time
tSU:DAT Input data setup time
tHD:DAT Input data hold time
tSU:STO STOP condition setup time
tHD:STO STOP condition setup time
tDH Output data hold time
tR SDA and SCL rise time
(Note 15)
Measured at the 70% of VCC crossing.
600
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window.
0
From 30% to 70% of VCC
20 +
0.1 * Cb
tF SDA and SCL fall time
(Note 15)
From 70% to 30% of VCC
20 +
0.1 * Cb
Cb Capacitive loading of SDA or SCL
(Note 15)
Total on-chip and off-chip
10
Rpu
(Note 15)
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF.
chip For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ.
1
tWC Non-volatile Write cycle time
(Notes 14)
12
tSU:A
tHD:A
A0, A1 setup time
A0, A1 hold time
Before START condition
After STOP condition
600
600
MAX
250
250
400
20
SDA vs SCL Timing
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
ms
ns
ns
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tR
tHD:DAT
tAA tDH
tSU:STO
tBUF
5 FN8241.2
August 15, 2005
5 Page 
ISL95711
Example 1
Writing a new value (77h) to the IVR:
Write to ACR first
01010000A00000010A00000000A
Then, write to IVR
01010000A00000000A01110111A
NOTE: The WR will also reflect this new value since both registers get written to at the same time)
Example 2
Reading from the WR:
Write to the ACR first (to index the WR)
01010000A00000010A10000000A
Then, Set the WR address
01010000A00000000A
Read from the WR
01010001Ax x x x x x x x
NOTE: A = acknowledge, x = data bit read
11 FN8241.2
August 15, 2005
11 Page | ||
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| PDF Descargar | [ Datasheet ISL95711.PDF ] | |
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