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PDF ISL6564 Data sheet ( Hoja de datos )
| Número de pieza | ISL6564 | |
| Descripción | Multiphase PWM Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
December 27, 2004
ISL6564
FN9156.2
Multi-Phase PWM Controller with Linear
6-bit DAC Capable of Precision rDS(ON) or
DCR Differential Current Sensing
The ISL6564 is a Multi-phase PWM controller which controls
microprocessor core voltage regulation by driving up to 4
synchronous-rectified buck channels. It features a high
bandwidth control loop to provide optimal response to the load
transients. With switching frequency up to 1.5MHz per phase,
the ISL6564 based voltage regulator requires minimum
components and PCB area in DC/DC converter application.
The ISL6564 senses current by utilizing patented techniques
to measure the voltage across the on resistance, rDS(on), of
the lower MOSFETs or DCR of the output inductor during
their conduction intervals. Current sensing provides the
needed signals for precision droop, channel-current
balancing, and overcurrent protection.
A unity gain, differential amplifier is provided for remote
voltage sensing. Any potential difference between remote
and local grounds can be completely eliminated using the
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The threshold-
sensitive enable input is available to accurately coordinate
the start up of the ISL6564 with any other voltage rail.
Dynamic-VID™ technology allows seamless on-the-fly VID
changes. The offset pin allows accurate voltage offset
settings that are independent of VID setting. The ISL6564
uses a 5V bias and has a built-in shunt regulator to allow
12V bias using only a small external limiting resistor.
Ordering Information
PART NUMBER TEMP. (°C) PACKAGE PKG. DWG. #
ISL6564CR
0 to 70 40 Ld 6x6 QFN L40.6x6
ISL6564CR-T
0 to 70 40 Ld 6x6 QFN L40.6x6
ISL6564CRZ (Note)
0 to70
40 Ld 6x6 QFN L40.6x6
(Pb-free)
ISL6564CRZ-T
(Note)
0 to 70 40 Ld 6x6 QFN L40.6x6
(Pb-free)
ISL6564IR
-40 to 85 40 Ld 6x6 QFN L40.6x6
ISL6564IR-T
-40 to 85 40 Ld 6x6 QFN L40.6x6
ISL6564IRZ (Note)
-40 to 85 40 Ld 6x6 QFN L40.6x6
(Pb-free)
ISL6564IRZ-T (Note) -40 to 85 40 Ld 6x6 QFN L40.6x6
(Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Precision Multi-Phase Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy
- Adjustable Reference-Voltage Offset
• Precision rDS(ON) or DCR Current Sensing
- Accurate Load-Line Programming
- Accurate Channel-Current Balancing
- Differential Current Sense
- Low-Cost, Lossless Current Sensing
• Internal Shunt Regulator for 5V or 12V Biasing
• Microprocessor Voltage Identification Input
- Self clocked Dynamic VID™ control technology
- 6-Bit VID Input
- 0.525V to 1.300V in 12.5mV Steps
• Threshold-Sensitive Enable Function for power
sequencing control
• Overcurrent Protection
• Overvoltage Protection
- No Additional External Components Needed
- OVP Pin to drive Crowbar Device
• 1, 2, 3, or 4 Phase Operation
• Up to 1.5MHz per phase Operation (>6MHz Ripple)
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-Free Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6564
Typical Application for Voltage Regulation without Droop Using DCR Sensing
VIDPGOOD
PGOOD
OVP
VID5
VID4
VID3
VID2
VID1
VID0
DRVEN
+5V
FB COMP REF
IDROOP
VDIFF
DAC
VSEN
RGND
VCC
ENLL
EN
ISL6564
ISEN1+
ISEN1-
PWM1
PWM2
OFS
FS
IOUT
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
GND
PWM4
ISEN4+
ISEN4-
NTC
NETWORK
VOLTAGE PROPOTIONAL
TO LOAD CURRENT
+12V
VCC
BOOT
UGATE
PVCC
PWM
ISL6612
DRIVER
PHASE
LGATE
GND
VIN
+12V
VCC
BOOT
PVCC
PWM
UGATE
ISL6612
DRIVER
PHASE
LGATE
GND
VIN
+12V
VCC
PVCC
PWM
BOOT
UGATE
ISL6612
DRIVER
PHASE
LGATE
GND
VIN
+12V
VCC
BOOT
PVCC
PWM
UGATE
ISL6612
DRIVER
PHASE
LGATE
GND
VIN
µP
LOAD
5 FN9156.2
December 27, 2004
5 Page 
ISL6564
PGOOD
PGOOD is used as an indication of the end of soft-start per
the microprocessor specification. It is an open-drain logic
output that is low impedance until the soft-start is completed.
It will be pulled low again once the undervoltage point is
reached.
OFS
The OFS pin provides a means to program a dc offset
current for generating a dc offset voltage at the REF input.
The offset current is generated via an external resistor and
precision internal voltage references. The polarity of the
offset is selected by connecting the resistor to GND or VCC.
For no offset, the OFS pin should be left unterminated.
OVP
Overvoltage protection pin. This pin pulls to VCC and is
latched when an overvoltage condition is detected. Connect
this pin to the gate of an SCR or MOSFET tied from VIN or
VOUT to ground to prevent damage to the load. This pin may
be pulled above VCC as high as 15V to ground with an
external resistor. However, it is only capable of pulling low
when VCC is above 2V.
DRVEN
Driver enable pin. This pin can be used to enable the drivers
which have enable pins such as ISL6605 or ISL6608. If
ISL6564 is used with Intersil ISL6612 drivers, it’s not
necessary to use this pin.
IDROOP and IOUT
IDROOP and IOUT are the output pins of sensed average
channel current which is proportional to load current. They
are designed for flexible application purposes.
In the application which does not require loadline, leave
IDROOP pin open. In the application which requires load
line, connect IDROOP pin to FB so that the sensed average
current will flow through the resistor between FB and VDIFF
to create a voltage drop which is proportional to load current.
IOUT is typically used for load current indication.
Operation
Multi-Phase Power Conversion
Microprocessor load current profiles have changed to the
point that the advantages of multi-phase power conversion
are impossible to ignore. The technical challenges
associated with producing a single-phase converter which is
both cost-effective and thermally viable have forced a
change to the cost-saving approach of multi-phase. The
ISL6564 controller helps reduce the complexity of
implementation by integrating vital functions and requiring
minimal output components. The block diagrams on pages
3, 4, 5 and 6 provide top level views of multi-phase power
conversion using the ISL6564 controller.
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
IL1, 7A/DIV
PWM2, 5V/DIV
PWM1, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-to-
peak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the dc components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
IPP = (---V----I--N-----–---L--V--f--OS----U-V----TI--N-)----V----O----U-----T-
(EQ. 1)
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and fS is the switching frequency.
11 FN9156.2
December 27, 2004
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ISL6564.PDF ] | |
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