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Número de pieza | RTD2513 | |
Descripción | (RTD2513 / RTD2523) Flat Panel Display Controller | |
Fabricantes | Realtek | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de RTD2513 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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RTD2523/2513
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RTD2523/2513
Flat Panel Display Controller
Confidential
Revision 0.18
March 19, 2004
1 page Realtek
RTD2523/2513
(I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground)
n ADC: 15 pins
Name
ADC_GND
ADC_REFIO
ADC_VDD
BLUE+
BLUE-
ADC_GND
SOG/ADC_TEST
GREEN+
GREEN-
ADCB_VDD
RED+
RED-
ADC_GND
ADC_GND
ADC_VDD
AHS
AVS
I/O Pin No
Description
Note
AG 27 ADC ground
AP 28 ADC band-gap voltage de-coupling
1.20V
AP 29 Analog power
(3.3V)
AI 30 Analog input from BLUE channel
AI 31 Analog input ground from BLUE channel
AG 32 ADC ground
AIO 33 SOG in/ADC test pin
AI 34 Analog input from GREEN channel
AI 35 Analog input ground from GREEN
channel
AP 36 Analog power
(3.3V)
AI 37 Analog input from RED channel
AI 38 Analog input ground from RED channel
AG 39 Analog ground
AG 40 Analog ground
AP 41 Analog power
(3.3V)
AI 42 Analog HS input
(10), (4), (5)
AI 43 Analog VS input
(2), (4), (5)
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n PLL: 8 pins
Name
XO
XI
DPLL_GND
DPLL_VDD
APLL_VDD
PLL_TEST1
PLL_TEST2
APLL_GND
I/O Pin No
Description
Note
AI 1 Reference clock output
AO 2 Reference clock input
AG 3 Ground for digital PLL
AP 4 Power for digital PLL
(3.3V)
AP 5 Power for multi-phase PLL
(3.3V)
AIO 6 Test Pin 1 / IRQ#
3.3V tolerance
AIO 7 Test Pin 2/Power-on-latch for crystal out
Frequency
AG 8 Ground for multi-phase PLL
n Control Interface: 7 pins
Name
I/O Pin No
SDIO [0]
IO 54
SDIO [1] / TCON [4] /
BBLU [0]
SDIO [2] / TCON [3] /
BBLU [1]
SDIO [3] / PWM2 /
TCON [2]
SCLK
SCSB
RESET
IO
IO
IO
I
I
O
53
52
51
50
111
56
Description
Serial control I/F data in / Parallel port data
[0]
Parallel port data [1] / TCON [4] / TTL
BBLU [0]
Parallel port data [2] / TCON [3] / TTL
BBLU [1]
Parallel port data [1] / TCON [4] / PWM2
Note
(2), (3), / 2mA
(1), (2), (3), / 2mA
(1), (2), (3), / 2mA
(1), (2), (3), / 2mA
Serial control I/F clock
Serial control I/F chip select
RESET output for Micron
(2), (3), (5)
(2), (3), (5)
(2), (5), (6) / 2mA
5
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Realtek
4. Functional Description
RTD2523/2513
4.1 Input
Digital Input (ITU 656)
RTD is designed to connect the interface of digital signal from video decoder. Input data is latched
within a capture window defined in registers. The timing scheme designed for input devices are
showed in the following diagram.
There are not H sync、V sync signals provided by the video decoder with ITU BT.656, these
synchronal signals have to be generated by decoding the EAV & SAV timing reference signals.
VGBCLK
VGB_R(Byte)
xxx
U0 Y0 V0 Y1 U2
Figure 4 Input YUV 4:2:2(8-bits) Timing
Only 254 of possible 256 8-bit words may be used to express a signal value, 0 and 255 are reserved for
data identification purposes. Video 8 data stream is as below:
Blanking Timing reference 720 pixels YUV 422 DATA
period
code
… 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 …
Cbn: U(B-Y) colour difference component
Yn : luminance component
Crn: V(R-Y) colour difference component
Timing reference Blanking
code period
Cr718 Y719 FF 00 00 EAV 80 10 …
SAV/EAV format
Bit 7 Bit 6(F)
1 Field bit
1st field F=0
2nd field F=1
Bit 5(V)
Bit 4(H) Bit 3(P3) Bit 2(P2) Bit 1(P1) Bit 0(P0)
Vertical blanking bit V=1 H=0 in SAV Protection bits
Active video V=0
H=1 in EAV
Hardware can recognize the occurrence of EAV & SAV by detecting the 0xff , 0x00 , 0x00 data
sequence, and then generate the Hsync、Vsync、Field signals internally by decoding the fourth word
of the timing reference signal(EAV、SAV). F & V change state synchronously with the EAV(End of
active video) reference code at the beginning of the digital line.
Bits P0, P1, P2, P3, have states dependent on the states of the bits F, V and H as shown below. At the
receiver this permits one-bit errors to be corrected and two-bits errors to be detected.
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet RTD2513.PDF ] |
Número de pieza | Descripción | Fabricantes |
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