|
|
PDF ISL54053 Data sheet ( Hoja de datos )
| Número de pieza | ISL54053 | |
| Descripción | SPDT Analog Switch | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL54053 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
Ultra Low ON-Resistance, Low Voltage, Single
Supply, SPDT Analog Switch
ISL54053
The Intersil ISL54053 device is a low ON-resistance, low
voltage, bidirectional, single pole/double throw (SPDT)
analog switch designed to operate from a single +1.8V
to +5.5V supply. Targeted applications include battery
powered equipment which benefit from low rON (0.8Ω)
and fast switching speeds (tON = 24ns, tOFF = 10ns).
The digital logic input is 1.8V logic compatible when
using a single +3.0V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins
may be limited and digital geometries are not well
suited to analog switch performance. This part may be
used to “mux-in” additional functionality while reducing
ASIC design risk. The ISL54053 is offered in the 6 Ld
1.2mmx1.0mmx0.5mm µTDFN and 6 Ld SOT-23
packages, alleviating board space limitations.
The ISL54053 is a committed SPDT that consists of one
normally open (NO) and one normally closed (NC)
switch. This configuration can also be used as a 2-to-1
multiplexer.
TABLE 1. FEATURES AT A GLANCE
ISL54053
Number of Switches
1
SW SPDT or 2-1 MUX
1.8V rON
1.8V tON/tOFF
3V rON
3V tON/tOFF
5V rON
5V tON/tOFF
Packages
2.3Ω
68ns/45ns
1.1Ω
29ns/12ns
0.8Ω
24ns/10ns
6 Ld μTDFN, 6 Ld SOT-23
Features
• Drop In replacement for the NLAS5123
• ON-resistance (rON)
- VCC = +5.0V. . . . . . . . . . . . . . . . . . . . .
- VCC = +3.0V. . . . . . . . . . . . . . . . . . . . .
- VCC = +1.8V. . . . . . . . . . . . . . . . . . . . .
0.8Ω
1.1Ω
2.3Ω
• rON matching between channels . . . . . . . . . 0.004Ω
• rON flatness (+4.5V supply) . . . . . . . . . . . . 0.25Ω
• Single supply operation . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V supply)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . 24ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns
• Guaranteed break-before-make
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . >6kV
• 1.8V CMOS logic compatible (+3V supply)
• Available in 6 Ld µTDFN and 6Ld SOT-23 Packages
• Pb-free (RoHS compliant)
Applications
• Battery powered, handheld, and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Portable test and measurement
• Medical equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
October 19, 2009
FN6460.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL54053
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 9),
Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
COM ON Capacitance,
CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 7)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
25 - 48 -
pF
Full -
- 0.5
V
Full 1.4
-
-
V
Full -0.1
-
0.1
μA
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 9),
Unless Otherwise Specified. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
ON-Resistance, rON
Full
V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V
to V+, (See Figure 5, Note 13)
25
Full
0 - V+
- 2.33 -
- 2.54 -
V
Ω
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω,
CL = 35pF (See Figure 1, Note 13)
25
Full
- 68 -
- 93 -
ns
ns
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω,
25
- 45 -
CL = 35pF (See Figure 1, Note 13)
Full - 71 -
ns
ns
Break-Before-Make Time
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω,
Full
-
15
-
Delay, tD
CL = 35pF (See Figure 3, Note 13)
Charge Injection, Q
VG = 0, RG = 0Ω, CL = 1.0nF (See Figure 2) 25
- 18 -
DIGITAL INPUT CHARACTERISTICS
ns
pC
Input Voltage Low, VINL
Full -
- 0.4
V
Input Voltage High, VINH
Full 1 - -
V
NOTES:
9. VIN = input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data
sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal
range.
13. Limits established by characterization and are not production tested.
5 FN6460.3
October 19, 2009
5 Page 
ISL54053
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E AB
PIN 1
REFERENCE
2X 0.10 C
2X 0.10 C
TOP VIEW
D
0.10 C
7X 0.08 C
DETAIL A
A
A1 A3
SIDE VIEW
C
SEATING
PLANE
DETAIL B
1
L1
4X
e
5X
3L
64
BOTTOM VIEW
b 6X
0.10 C A B
0.05 C NOTE 3
0.1x45°
CHAMFER
A1 A3
DETAIL A
DETAIL B PIN 1 LEAD
L6.1.2x1.0A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN NOMINAL MAX
NOTES
A
0.45 0.50 0.55
-
A1 - - 0.05 -
A3 0.127 REF -
b
0.15 0.20 0.25
5
D
0.95 1.00 1.05
-
E
1.15 1.20 1.25
-
e
0.40 BSC
-
L
0.30 0.35 0.40
-
L1 0.40 0.45 0.50 -
N 62
Ne 3 3
θ 0 - 12 4
NOTES:
Rev. 2 8/06
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
1.00
1.40
0.20
0.45
0.30
0.35
0.20
0.40
LAND PATTERN 10
11 FN6460.3
October 19, 2009
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL54053.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL54050 | Ultra Low ON-Resistance Dual SDPT Analog Switch | Intersil Corporation |
| ISL54051 | (ISL54051 / ISL54052) Single SPST Analog Switches | Intersil Corporation |
| ISL54052 | (ISL54051 / ISL54052) Single SPST Analog Switches | Intersil Corporation |
| ISL54053 | SPDT Analog Switch | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |