PDF HI5667 Data sheet ( Hoja de datos )

Número de pieza	HI5667
Descripción	60MSPS A/D Converter
Fabricantes	Intersil Corporation
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Hay una vista previa y un enlace de descarga de HI5667 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas
No Preview Available ! ® cN1o-On8t8aR8DcE-tIaCNOotOTaBuEMSrSROTMhSeLeEcIEeLNhTtnDoEirEcPwDaRlwRSOwEuD.PpiUnpLtCoAeTrrCtsEiClM.ecnEotmNeTr/tastc March 2003 HI5667 FN4584.2 8-Bit, 60MSPS A/D Converter with Internal Voltage Reference The HI5667 is a monolithic, 8-bit, analog-to-digital converter fabricated in a CMOS process. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its high sample clock rate is made possible by a fully differential pipelined architecture with both an internal sample and hold and internal band-gap voltage reference. Features • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 60MSPS • 7.7Bits at fIN = 10MHz, fS = 60MSPS • Low Power at 60MSPS . . . . . . . . . . . . . . . . . . . . 350mW • Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz • On-Chip Sample and Hold • Internal 2.5V Band-Gap Voltage Reference The 250MHz Full Power Input Bandwidth and superior high frequency performance of the HI5667 converter make it an excellent choice for implementing Digital IF architectures in communications applications. The HI5667 has excellent dynamic performance while consuming only 350mW power at 60MSPS. Data output latches are provided which present valid data to the output bus with a latency of 7 clock cycles. • Fully Differential or Single-Ended Analog Input • Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V • TTL/CMOS Compatible Digital Inputs • CMOS Compatible Digital Outputs. . . . . . . . . . 3.0V/5.0V • Offset Binary or Two’s Complement Output Format Applications . Part Number Information • Digital Communication Systems • QAM Demodulators PART www.DataSheet4U.com NUMBER HI5667/6CB TEMP. RANGE (oC) PACKAGE 0 to 70 28 Ld SOIC PKG. NO. M28.3 SAMPLING RATE (MSPS) 60 • Professional Video Digitizing • Medical Imaging • High Speed Data Acquisition HI5667/6CA HI5667EVAL2 0 to 70 28 Ld SSOP M28.15 25 Evaluation Board 60 60 Pinout HI5667 (SOIC, SSOP) TOP VIEW DVCC1 1 DGND 2 DVCC1 3 DGND 4 AVCC 5 AGND 6 VREF IN VREF OUT VIN+ 7 8 9 VIN- 10 VDC 11 AGND 12 AVCC 13 OE 14 28 NC 27 NC 26 D0 25 D1 24 D2 23 DVCC2 22 CLK 21 DGND 20 D3 19 D4 18 D5 17 D6 16 D7 15 DFS 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 1 page HI5667 Electrical Specifications ACVL C=C10=pDFV; CTAC1==255o.0CV;,DDifVfeCrCen2t=ial3A.0nVa;loVgRIEnFpIuNt;=TVypRiEcaFlOVUaTl;ufeSs = 60MSPS at 50% Duty Cycle; are Test Results at 25oC, Unless Otherwise Specified (Continued) PARAMETER Reference Temperature Coefficient REFERENCE VOLTAGE INPUT Reference Voltage Input, VREFIN Total Reference Resistance, RREFIN Reference Input Current, IREFIN DC BIAS VOLTAGE DC Bias Voltage Output, VDC Maximum Output Current DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Three-State Leakage Current, IOZ Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Three-State Leakage Current, IOZ Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Hold, tH Data Output Delay, tOD Data Output Enable Time, tEN Data Output Enable Time, tDIS Data Latency, tLAT Power-Up Initialization Sample Clock Pulse Width (Low) Sample Clock Pulse Width (High) Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVCC Digital Supply Voltage, DVCC1 Digital Output Supply Voltage, DVCC2 Total Supply Current, ICC Analog Supply Current, AICC Digital Supply Current, DICC Output Supply Current, DICC2 Power Dissipation Offset Error Sensitivity, ∆VOS Gain Error Sensitivity, ∆FSE NOTES: TEST CONDITIONS CLK, DFS, OE CLK, DFS, OE CLK, DFS, OE, VIH = 5V CLK, DFS, OE, VIL = 0V IOH = 100µA; DVCC2 = 5V IOL = 100µA; DVCC2 = 5V VO = 0/5V; DVCC2 = 5V IOH = 100µA; DVCC2 = 3V IOL = 100µA; DVCC2 = 3V VO = 0/5V; DVCC2 = 3V For a Valid Sample (Note 2) Data Invalid Time (Note 2) fS = 60MSPS fS = 60MSPS fS = 60MSPS At 3.0V At 5.0V fIN = 10MHz and DFS = “0” fIN = 10MHz and DFS = “0” fIN = 10MHz and DFS = “0” fIN = 10MHz and DFS = “0” fIN = 10MHz and DFS = “0” AVCC or DVCC = 5V ±5% AVCC or DVCC = 5V ±5% MIN TYP MAX - 120 - - 2.5 - - 2.5 - -1- - 3.0 - - - 0.2 2.0 - - - - 0.8 -10.0 - +10.0 -10.0 - +10.0 -7- 4.0 - - - - 0.8 -10 ±1 10 2.4 - - - - 0.5 -10 ±1 10 - 10 - -5 -5 -5 -6 -5 -5 -- -- 7.5 8.33 7.5 8.33 - ±5 - - - - - - 7 20 - - - 4.75 5.0 5.25 4.75 5.0 5.25 2.7 3.0 3.3 4.75 5.0 5.25 - 70 92 - 47 63 - 21 25 - 24 - 346 452 - ±0.175 - - ±0.025 - 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. UNITS ppm/oC V kΩ mA V mA V V µA µA pF V V µA V V µA pF ns psRMS ns ns ns ns Cycles Cycles ns ns % V V V V mA mA mA mA mW LSB LSB 5 5 Page

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