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PDF AM75PDL191BHHA Data sheet ( Hoja de datos )
| Número de pieza | AM75PDL191BHHA | |
| Descripción | (AM75PDL191BHHA / AM75PDL193BHHA) Simultaneous Read/Write Flash Memory | |
| Fabricantes | AMD | |
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Am75PDL191BHHa/
Am75PDL193BHHa
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 30898 Revision A Amendment +2 Issue Date February 6, 2004
1 page  
ADVANCE INFORMATION
PSRAM FEATURES
■ Organized: 2M x 16 bit
■ Power Supply voltage of 2.7 to 3.1 V
■ Three state outputs
■ Compatible with Low Power SRAM
■ Deep power Down: Memory cell data holds invalid
February 6, 2004
Am75PDL191BHHa/Am75PDL193BHHa
3
5 Page 
ADVANCE INFORMATION
PSRAM AC Characteristics . . . . . . . . . . . . . . . . . 66
CE#s Timing ........................................................................... 66
Figure 12. Timing Diagram for Alternating
Between Pseudo SRAM to Flash.................................................... 66
Figure 13. Timing Waveform of Power-up ...................................... 66
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67
Read-Only Operations – Am29PDL127H ............................... 67
Read-Only Operations – Am29PDL129H ............................... 67
Figure 14. Read Operation Timings ................................................ 68
Figure 15. Page Read Operation Timings....................................... 68
Hardware Reset (RESET#) .................................................... 69
Figure 16. Reset Timings ................................................................ 69
Erase and Program Operations .............................................. 70
Figure 17. Program Operation Timings........................................... 71
Figure 18. Accelerated Program Timing Diagram........................... 71
Figure 19. Chip/Sector Erase Operation Timings ........................... 72
Figure 20. Back-to-back Read/Write Cycle Timings ....................... 73
Figure 21. Data# Polling Timings (During Embedded Algorithms).. 73
Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 74
Figure 23. DQ2 vs. DQ6.................................................................. 74
Temporary Sector Unprotect .................................................. 75
Figure 24. Temporary Sector Unprotect Timing Diagram ............... 75
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram .............................................................. 76
Alternate CE# Controlled Erase and Program Operations ..... 77
Figure 26. Flash Alternate CE# Controlled Write (Erase/Program)
Operation Timings........................................................................... 78
Erase And Programming Performance . . . . . . . . 79
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 79
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 79
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 79
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 80
Table 1. Am29DL640H Device Bus Operations ..............................80
Word/Byte Configuration ........................................................ 80
Requirements for Reading Array Data ................................... 80
Writing Commands/Command Sequences ............................ 81
Accelerated Program Operation .......................................... 81
Autoselect Functions ........................................................... 81
Simultaneous Read/Write Operations with Zero Latency ....... 81
Standby Mode ........................................................................ 81
Automatic Sleep Mode ........................................................... 81
RESET#: Hardware Reset Pin ............................................... 82
Output Disable Mode .............................................................. 82
Table 2. Am29DL640H Sector Architecture ....................................82
Table 3. Bank Address ....................................................................85
Autoselect Mode ..................................................................... 85
Sector/Sector Block Protection and Unprotection .................. 87
Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................87
Write Protect (WP#) ................................................................ 87
Table 6. WP#/ACC Modes ..............................................................88
Temporary Sector Unprotect .................................................. 88
Figure 1. Temporary Sector Unprotect Operation........................... 88
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 89
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 90
Figure 3. SecSi Sector Protect Verify.............................................. 91
Hardware Data Protection ...................................................... 91
Low VCC Write Inhibit ......................................................... 91
Write Pulse “Glitch” Protection ............................................ 91
Logical Inhibit ....................................................................... 91
Power-Up Write Inhibit ......................................................... 91
Common Flash Memory Interface (CFI) . . . . . . . 91
Command Definitions . . . . . . . . . . . . . . . . . . . . . 95
Reading Array Data ................................................................ 95
Reset Command ..................................................................... 95
Autoselect Command Sequence ............................................ 95
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 95
Word Program Command Sequence ...................................... 96
Unlock Bypass Command Sequence .................................. 96
Figure 4. Program Operation ......................................................... 97
Chip Erase Command Sequence ........................................... 97
Sector Erase Command Sequence ........................................ 97
Figure 5. Erase Operation.............................................................. 98
Erase Suspend/Erase Resume Commands ........................... 98
Write Operation Status . . . . . . . . . . . . . . . . . . . 100
DQ7: Data# Polling ............................................................... 100
Figure 6. Data# Polling Algorithm ................................................ 100
RY/BY#: Ready/Busy# .......................................................... 101
DQ6: Toggle Bit I .................................................................. 101
Figure 7. Toggle Bit Algorithm...................................................... 101
DQ2: Toggle Bit II ................................................................. 102
Reading Toggle Bits DQ6/DQ2 ............................................. 102
DQ5: Exceeded Timing Limits .............................................. 102
DQ3: Sector Erase Timer ..................................................... 102
Table 12. Write Operation Status ................................................. 103
Absolute Maximum Ratings . . . . . . . . . . . . . . . 104
Figure 8. Maximum Negative Overshoot Waveform .................... 104
Figure 9. Maximum Positive Overshoot Waveform...................... 104
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 10. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ........................................................... 106
Figure 11. Typical ICC1 vs. Frequency .......................................... 106
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 12. Test Setup.................................................................. 107
Figure 13. Input Waveforms and Measurement Levels ............... 107
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 108
Read-Only Operations ......................................................... 108
Figure 14. Read Operation Timings ............................................. 108
Hardware Reset (RESET#) .................................................. 109
Figure 15. Reset Timings ............................................................. 109
Erase and Program Operations ............................................ 110
Figure 16. Program Operation Timings........................................ 111
Figure 17. Accelerated Program Timing Diagram........................ 111
Figure 18. Chip/Sector Erase Operation Timings ........................ 112
Figure 19. Back-to-back Read/Write Cycle Timings .................... 113
Figure 20. Data# Polling Timings (During Embedded Algorithms) 113
Figure 21. Toggle Bit Timings (During Embedded Algorithms).... 114
Figure 22. DQ2 vs. DQ6............................................................... 114
Temporary Sector Unprotect ................................................ 115
Figure 23. Temporary Sector Unprotect Timing Diagram ............ 115
Figure 24. Sector/Sector Block Protect and
Unprotect Timing Diagram ........................................................... 116
Alternate CE# Controlled Erase and Program Operations ... 117
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings........................................................................ 118
pSRAM AC CHaracteristics . . . . . . . . . . . . . . . . 119
Functional Description .......................................................... 119
Absolute Maximum Ratings .................................................. 119
February 6, 2004
Am75PDL191BHHa/Am75PDL193BHHa
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