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PDF AM75DL9608HG Data sheet ( Hoja de datos )
| Número de pieza | AM75DL9608HG | |
| Descripción | Simultaneous Operation Flash Memories | |
| Fabricantes | AMD | |
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Am75DL9608HG
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 30772 Revision A Amendment +1 Issue Date November 17, 2003
1 page  
ADVANCE INFORMATION
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Memory Block Diagram . . . . . . . . . . . . . . . 7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 8
Special Package Handling Instructions .................................... 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
MCP Device Bus Operations . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations—Flash Word Mode .................... 11
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Requirements for Reading Array Data ................................... 12
Writing Commands/Command Sequences ............................ 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13
Table 2. Am29DL640H Sector Architecture ....................................14
Table 3. Am29DL640H Bank Address ............................................17
Table 4. Am29DL640H SecSi™ Sector Addresses .......................17
Table 5. Am29DL320G Top Boot Sector Addresses .....................18
Table 6. Am29DL320G Top Boot SecSiTM Sector Addresses ........ 19
Table 7. Am29DL320G Bottom Boot Sector Addresses .................20
Table 8. Am29DL320G Bottom Boot SecSiTM Sector Addresses ... 21
Table 9. Am29DL640H Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................22
Table 10. Am29DL320G Top Boot Sector/Sector
Block Addresses for Protection/Unprotection ..................................23
Table 11. Am29DL320G Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................23
Write Protect (WP#) ................................................................ 24
Table 12. WP#/ACC Modes ............................................................24
Temporary Sector Unprotect .................................................. 24
Figure 1. Temporary Sector Unprotect Operation........................... 25
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 26
SecSi™ (Secured Silicon) Sector
SectorFlash Memory Region ................................................. 27
Table 13. SecSi Sector Programming ................................................27
Figure 3. SecSi Sector Protect Verify.............................................. 28
Hardware Data Protection ...................................................... 28
Common Flash Memory Interface (CFI) . . . . . . . 28
Table 14. Am29DL640H CFI Query Identification String ................ 29
Table 15. Am29DL640H System Interface String ........................... 29
Table 16. Am29DL640H Device Geometry Definition..................... 30
Table 17. Am29DL640H Primary Vendor-Specific
Extended Query .............................................................................. 31
Table 18. Am29DL320G CFI Query Identification String ................ 32
Table 19. Am29DL320G System Interface String ........................... 32
Table 20. Am29DL320G Device Geometry Definition..................... 33
Table 21. Am29DL320G Primary Vendor-Specific
Extended Query .............................................................................. 34
Flash Command Definitions . . . . . . . . . . . . . . . . 35
Reading Array Data ................................................................ 35
Reset Command ..................................................................... 35
Autoselect Command Sequence ............................................ 35
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 35
Program Command Sequence ............................................... 36
Figure 4. Program Operation .......................................................... 37
Chip Erase Command Sequence ........................................... 37
Sector Erase Command Sequence ........................................ 37
Figure 5. Erase Operation.............................................................. 38
Erase Suspend/Erase Resume Commands ........................... 38
Table 22. Am29DL640H and Am29DL320G Command Definitions 39
Flash Write Operation Status . . . . . . . . . . . . . . . 40
DQ7: Data# Polling ................................................................. 40
Figure 6. Data# Polling Algorithm .................................................. 40
DQ6: Toggle Bit I .................................................................... 41
Figure 7. Toggle Bit Algorithm........................................................ 41
DQ2: Toggle Bit II ................................................................... 42
Reading Toggle Bits DQ6/DQ2 ............................................... 42
DQ5: Exceeded Timing Limits ................................................ 42
DQ3: Sector Erase Timer ....................................................... 42
Table 23. Write Operation Status ................................................... 43
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 44
Figure 8. Maximum Negative Overshoot Waveform ...................... 44
Figure 9. Maximum Positive Overshoot Waveform........................ 44
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 45
CMOS Compatible ..................................................................... 45
Figure 10. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 46
Figure 11. Typical ICC1 vs. Frequency ............................................ 46
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 47
Figure 12. Standby Current ISB CMOS ......................................... 47
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Test Setup.................................................................... 48
Figure 14. Input Waveforms and Measurement Levels ................. 48
Flash AC Characteristics . . . . . . . . . . . . . . . . . . 49
Pseudo SRAM CE#s Timing ...................................................... 49
Figure 15. Timing Diagram for Alternating
Between Pseudo SRAM to Flash................................................... 49
Read-Only Operations .............................................................. 50
Figure 16. Read Operation Timings ............................................... 50
Hardware Reset (RESET#) ....................................................... 51
Figure 17. Reset Timings ............................................................... 51
Erase and Program Operations ................................................. 52
Figure 18. Program Operation Timings.......................................... 53
Figure 19. Accelerated Program Timing Diagram.......................... 53
Figure 20. Chip/Sector Erase Operation Timings .......................... 54
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 55
Figure 22. Data# Polling Timings (During Embedded Algorithms). 55
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 56
Figure 24. DQ2 vs. DQ6................................................................. 56
Temporary Sector Unprotect ..................................................... 57
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 57
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 58
Alternate CE#f Controlled Erase and Program Operations ....... 59
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 60
Pseudo SRAM AC Characteristics . . . . . . . . . . . 61
Power Up Time .......................................................................... 61
Read Cycle ................................................................................ 61
Figure 28. Pseudo SRAM Read Cycle—Address Controlled......... 61
Figure 29. Pseudo SRAM Read Cycle........................................... 62
Write Cycle ................................................................................ 63
Figure 30. Pseudo SRAM Write Cycle—WE# Control ................... 63
Figure 31. Pseudo SRAM Write Cycle—CE1#s Control ................ 64
Figure 32. Pseudo SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 65
November 17, 2003
Am75DL9608HG
3
5 Page 
ADVANCE INFORMATION
PIN DESCRIPTION
A18–A0
= 19 Address Inputs (Common)
A21–A19, A-1 = 4 Address Inputs (Flash)
DQ15–DQ0 = 16 Data Inputs/Outputs (Common)
CE#f1
= Flash Chip Enable 1
(Am29DL640H)
CE#f2
= Flash Chip Enable 2
(Am29DL320G)
CE#1s
= Pseudo SRAM Chip Enable 1
CE2s
= Pseudo SRAM Chip Enable 2
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (Pseudo SRAM)
LB#s
= Lower Byte Control (Pseudo SRAM)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
VCCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCCs
VSS
NC
= Pseudo SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
19
A18–A0
A21–A19
CE#f1
CE#f2
CE1#s
CE2s
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
DQ15–DQ0
RY/BY#
16
November 17, 2003
Am75DL9608HG
9
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