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PDF HI3338 Data sheet ( Hoja de datos )
| Número de pieza | HI3338 | |
| Descripción | CMOS R2R D/A Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
July 2004
HI3338
FN4134.3
8-Bit, CMOS R2R D/A Converter
The HI3338 family are CMOS high speed R2R voltage
output digital-to-analog converters. They can operate from a
single +5V supply, at video speeds, and can produce
“rail-to-rail” output swings. Internal level shifters and a pin for
an optional second supply provide for an output range below
digital ground.
The data complement control allows the inversion of input
data while the latch enable control provides either
feedthrough or latched operation. Both ends of the R2R
ladder network are available externally and may be
modulated for gain or offset adjustments. In addition, “glitch”
energy has been kept very low by segmenting and
thermometer encoding of the upper 3 bits.
The HI3338 is manufactured to give low dynamic power
dissipation, low output capacitance, and inherent latch-up
resistance.
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
HI3338KIB
www.DataSheet4U.com
HI3338KIBZ
(Note)
-40 to 85
-40 to 85
16 Ld SOIC
16 Ld SOIC
(Pb-free)
M16.3
M16.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Features
• CMOS Low Power (Typ) . . . . . . . . . . . . . . . . . . . . .100mW
• R2R Output, Segmented for Low “Glitch”
• CMOS/TTL Compatible Inputs
• Fast Settling (Typ) . . . . . . . . . . . . . . . . . . 20ns to 1/2 LSB
• Feedthrough Latch for Clocked or Unclocked Use
• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
• Data Complement Control
• High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . . 50MHz
• Unipolar or Bipolar Operation
• Linearity (INL)
- HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.75 LSB
• Pb-free Available
Applications
• TV/Video Display
• High Speed Oscilloscope Display
• Digital Waveform Generator
• Direct Digital Frequency Synthesis
• Wireless Communication
Pinout
HI3338 (SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
VSS 8
16 VDD
15 LE
14 COMP
13 VREF+
12 VOUT
11 VREF-
10 VEE
9 D0
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
HI3338
Pin Descriptions
PIN NAME
DESCRIPTION
1 D7 Most Significant Bit
2 D6 Input
3 D5 Data
4 D4 Bits
5 D3 (High = True)
6 D2
7 D1
8 VSS Digital Ground
9 D0 Least Significant Bit. Input Data Bit
10 VEE Analog Ground
11 VREF- Reference Voltage Negative Input
12 VOUT Analog Output
13 VREF+ Reference Voltage Positive Input
14 COMP Data Complement Control input. Active High
15 LE Latch Enable Input. Active Low
16 VDD Digital Power Supply, +5V
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 20) through D7 (weighted 27),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of VDD and VSS, are shifted to operate between VDD
and VEE. VEE optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the VDD
and VEE supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: tD2
gives the delay from the input changing to the output
changing (10%), while tSU2 and tH give the set up and hold
times (referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given tSU1 set up time to the LE falling edge,
and the tH hold time from the LE rising edge. The delay to
the output changing, tD1, is now referred to the LE falling
edge.
There is no need for a square wave LE clock; LE must only
meet the minimum tW pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus
the bottom “2R” resistor are returned to VREF- this is the
(-) full-scale reference. The “P” channel (pull up) transistor
of each driver is returned to VREF+, the (+) full-scale
reference.
In unipolar operation, VREF- would typically be returned to
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
that flows from VREF+ to VREF- (see VREF+ input current in
specifications), so VREF- should have a low impedance path
to ground.
In bipolar operation, VREF- would be returned to a negative
voltage (the maximum voltage rating to VDD must be
observed). VEE, which supplies the gate potential for the
output drivers, must be returned to a point at least as
negative as VREF-. Note that the maximum clocking speed
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to VREF-
with an input code of 00HEX (zero scale output), and an
output equal to 255/256 of VREF+ (referred to VREF-) with
an input code of FFHEX (full scale output). The difference
between the ideal and actual values of these two parameters
are the OFFSET and GAIN errors, respectively; see
Figure 3.
5
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