PDF AM49PDL640AG Data sheet ( Hoja de datos )

Número de pieza	AM49PDL640AG
Descripción	Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
Fabricantes	AMD
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No Preview Available ! Am49PDL640AG Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information www.DataSheet4U.com Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 30049 Revision A Amendment +5 Issue Date November 20, 2003 1 page PRELIMINARY TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram . . . . . . . . . . . . . . . . 6 PSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations . . . . . . . . . . . . . . . . . 9 Random Read (Non-Page Read) ........................................ 11 Page Mode Read ................................................................ 11 Table 2. Page Select .......................................................................11 Simultaneous Operation ......................................................... 11 Table 3. Bank Select .......................................................................11 Writing Commands/Command Sequences ............................ 11 Accelerated Program Operation .......................................... 12 Autoselect Functions ........................................................... 12 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 13 Table 4. Am29PDL640G Sector Architecture .................................13 Table 5. Bank Address ....................................................................14 Table 6. SecSiTM SectorSecure Sector Addresses .........................14 Table 7. Am29PDL640G Boot Sector/Sector Block Addresses for Pro- tection/Unprotection ........................................................................15 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 16 Persistent Sector Protection ................................................... 16 Persistent Protection Bit (PPB) ............................................ 16 Persistent Protection Bit Lock (PPB Lock) .......................... 16 Dynamic Protection Bit (DYB) ............................................. 16 Table 8. Sector Protection Schemes ...............................................17 Persistent Sector Protection Mode Locking Bit ................... 17 Password Protection Mode ..................................................... 17 Password and Password Mode Locking Bit ........................ 18 64-bit Password ................................................................... 18 Write Protect (WP#) ................................................................ 18 Persistent Protection Bit Lock .............................................. 18 High Voltage Sector Protection .............................................. 19 Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms ...................................................... 20 Temporary Sector Unprotect .................................................. 21 Figure 2. Temporary Sector Unprotect Operation........................... 21 SecSi™ (Secured Silicon) Sector SectorFlash Memory Region ................................................. 21 SecSi Sector Protection Bit ................................................. 22 Figure 3. SecSi Sector Protect Verify.............................................. 22 Hardware Data Protection ...................................................... 23 Low VCC Write Inhibit ......................................................... 23 Write Pulse “Glitch” Protection ............................................ 23 Logical Inhibit ...................................................................... 23 Power-Up Write Inhibit ......................................................... 23 Common Flash Memory Interface (CFI) . . . . . . . 23 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 27 Reading Array Data ................................................................ 27 Reset Command ..................................................................... 27 Autoselect Command Sequence ............................................ 27 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 28 Word Program Command Sequence ...................................... 28 Unlock Bypass Command Sequence .................................. 28 Figure 4. Program Operation ......................................................... 29 Chip Erase Command Sequence ........................................... 29 Sector Erase Command Sequence ........................................ 29 Erase Suspend/Erase Resume Commands ........................... 30 Figure 5. Erase Operation.............................................................. 30 Password Program Command ................................................ 30 Password Verify Command .................................................... 31 Password Protection Mode Locking Bit Program Command .. 31 Persistent Sector Protection Mode Locking Bit Program Com- mand ....................................................................................... 31 SecSi Sector Protection Bit Program Command .................... 31 PPB Lock Bit Set Command ................................................... 31 DYB Write Command ............................................................. 31 Password Unlock Command .................................................. 32 PPB Program Command ........................................................ 32 All PPB Erase Command ........................................................ 32 DYB Write Command ............................................................. 32 PPB Lock Bit Set Command ................................................... 32 PPB Status Command ............................................................ 32 PPB Lock Bit Status Command .............................................. 32 Sector Protection Status Command ....................................... 32 Table 13. Memory Array Command Definitions ............................. 33 Table 14. Sector Protection Command Definitions ........................ 34 Write Operation Status . . . . . . . . . . . . . . . . . . . . 35 DQ7: Data# Polling ................................................................. 35 Figure 6. Data# Polling Algorithm .................................................. 35 DQ6: Toggle Bit I .................................................................... 36 Figure 7. Toggle Bit Algorithm........................................................ 36 DQ2: Toggle Bit II ................................................................... 37 Reading Toggle Bits DQ6/DQ2 ............................................... 37 DQ5: Exceeded Timing Limits ................................................ 37 DQ3: Sector Erase Timer ....................................................... 37 Table 15. Write Operation Status ................................................... 38 pSRAM Power Down . . . . . . . . . . . . . . . . . . . . . . 39 Figure 8. State Diagram ................................................................. 39 Table 16. Standby Mode Characteristics ....................................... 39 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 40 Figure 9. Maximum Negative Overshoot Waveform ...................... 40 Figure 10. Maximum Positive Overshoot Waveform...................... 40 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 11. Test Setup.................................................................... 43 Figure 12. Input Waveforms and Measurement Levels ................. 43 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 pSRAM CE#s Timing .............................................................. 44 Figure 13. Timing Diagram for Alternating Between pSRAM to Flash .............................................................. 44 Read-Only Operations ........................................................... 45 Figure 14. Read Operation Timings ............................................... 45 Figure 15. Page Read Operation Timings...................................... 46 Hardware Reset (RESET#) .................................................... 47 Figure 16. Reset Timings ............................................................... 47 Erase and Program Operations .............................................. 48 Figure 17. Program Operation Timings.......................................... 49 Figure 18. Accelerated Program Timing Diagram.......................... 49 Figure 19. Chip/Sector Erase Operation Timings .......................... 50 November 20, 2003 Am49PDL640AG 3 5 Page PRELIMINARY ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49PDL640 A G a 70 N T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE N = Light Industrial (–25°C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations pSRAM VENDOR Blank = Etron a = Si-7 PROCESS TECHNOLOGY G = 0.17 µm Pseudo SRAM DEVICE DENSITY A = 16 Mbits AMD DEVICE NUMBER/DESCRIPTION Am49PDL640AG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Valid Combinations Order Number Package Marking Am49PDL640AG70N M49000001Y Am49PDL640AG85N Am49PDL640AGa70N T, S M49000001Z M49000004F Am29PDL640AGa85N M49000004G MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. November 20, 2003 Am49PDL640AG 9 11 Page

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