|
|
PDF AM49PDL129BH Data sheet ( Hoja de datos )
| Número de pieza | AM49PDL129BH | |
| Descripción | (AM49PDL127BH / AM49PDL129BH) Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS | |
| Fabricantes | AMD | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AM49PDL129BH (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Am49PDL127BH/
Am49PDL129BH
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
www.DataSheet4U.com
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 30452 Revision A Amendment +3 Issue Date December 16, 2003
1 page  
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29PDL127H/Am29PDL129H are 128 Mbit, 3.0
volt-only Page Mode and Simultaneous Read/Write Flash
memory devices organized as 8 Mwords. The word-wide
data (x16) appears on DQ15-DQ0. The devices can be pro-
grammed in-system or in standard EPROM programmers. A
12.0 V VPP is not required for write or erase operations.
The devices offer fast page access time of 25 and 30 ns,
with corresponding random access times of 65 and 85 ns,
respectively, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the de-
vices have separate chip enable (CE#f1, CE#f2), write
enable (WE#) and output enable (OE#) controls. Dual Chip
Enables allow access to two 64 Mbit partitions of the 128
Mbit memory space.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides simul-
taneous operation by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
PDL127 Configuration
Chip Enable Control
CE#f1
Bank
A
B
C
D
Sectors
16 Mbit (4 Kw x 8 and 32 Kw x 31)
48 Mbit (32 Kw x 96)
48 Mbit (32 Kw x 96)
16 Mbit (4 Kw x 8 and 32 Kw x 31)
PDL129H Configuration
Chip Enable Control
CE#f1
CE#f2
Bank
A
B
C
D
Sectors
16 Mbit (4 Kw x 8 and 32 Kw x 31)
48 Mbit (32 Kw x 96)
48 Mbit (32 Kw x 96)
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Page Mode Features
The page size is 8 words. After initial page access is accom-
plished, the page mode operation provides fast read access
speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V
to 3.3 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard. Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
December 16, 2003
Am49PDL127BH/Am49PDL129BH
3
5 Page 
ADVANCE INFORMATION
PIN DESCRIPTION
A20–A0
= 21 Address Inputs (Common)
A21 = Address Inputs (Flash)
A22 = Address Input (PDL127 only)
(Flash)
DQ15–DQ0 = 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash)
CE#f2
= Chip Enable 2 (Flash)
(PDL 129 only)
CE#1ps
= Chip Enable 1 (pSRAM)
CE2ps
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output and open drain.
When RY/BY# = VIH, the device is
ready to accept read operations and
commands. When RY/BY# = VOL,
the device is either executing an em-
bedded algorithm or the device is
executing a hardware reset opera-
tion.
UB#s
= Upper Byte Control (pSRAM)
LB#s
= Lower Byte Control (pSRAM)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Write Protect/Acceleration Input.
When WP/ACC#= VIL, the highest
and lowest two 4K-word sectors are
write protected regardless of other
sector protection configurations.
When WP/ACC#= VIH, these sector
are unprotected unless the DYB or
PPB is programmed. When
WP/ACC#= 12V, program and erase
operations are accelerated.
VCCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCCs
VSS
NC
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
LOGIC SYMBOL
21
A20–A0
A21
A22 (PDL127 Only)
CE#f1
DQ15–DQ0
CE#f2 (PDL129 Only)
CE#1ps
CE2ps
RY/BY#
OE#
WE#
WP#/ACC
RESET#
UB#s
LB#s
16
December 16, 2003
Am49PDL127BH/Am49PDL129BH
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM49PDL129BH.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AM49PDL129BH | (AM49PDL127BH / AM49PDL129BH) Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS | AMD |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |