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PDF AM49PDL127AH Data sheet ( Hoja de datos )
| Número de pieza | AM49PDL127AH | |
| Descripción | (AM49PDL127AH / AM49PDL129AH) Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM | |
| Fabricantes | AMD | |
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Am49PDL127AH/
Am49PDL129AH
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
www.DataSheet4U.com
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 30535 Revision A Amendment +1 Issue Date December 18, 2003
1 page  
ADVANCE INFORMATION
GENERAL DESCRIPTION (PDL129)
The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 8 Mwords. The word-wide data (x16) appears on
DQ15-DQ0. This device can be programmed in-system or in
standard EPROM programmers. A 12.0 V VPP is not re-
quired for write or erase operations.
The device offers fast page access time of 25 and 30 ns,
with corresponding random access times of 65 and 70 ns,
respectively, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the de-
vice has separate chip enable (CE#f1, CE#f2), write enable
(WE#) and output enable (OE#) controls. Dual Chip Enables
allow access to two 64 Mbit partitions of the 128 Mbit mem-
ory space.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides simul-
taneous operation by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
Chip Enable Configuration
CE#f1 Control
CE#f2 Control
Bank 1A
48 Mbit (32 Kw x 96)
Bank 2A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 1B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 2B
48 Mbit (32 Kw x 96)
Page Mode Features
The page size is 8 words. After initial page access is accom-
plished, the page mode operation provides fast read access
speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V
to 3.3 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard. Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
December 18, 2003
Am49PDL127AH/Am49PDL129AH
3
5 Page 
ADVANCE INFORMATION
CONNECTION DIAGRAM–PDL127
73-Ball FBGA
Top View
A1 A10
NC NC
B1
B5 B6
B10
NC NC NC NC
C1 C3 C4 C5 C6 C7 C8
NC A7 LB# WP#/ACC WE# A8 A11
D2 D3 D4 D5 D6 D7 D8 D9
A3 A6 UB# RESET# CE2ps A19 A12 A15
E2 E3 E4 E5 E6 E7 E8 E9
A2 A5 A18 RY/BY# A20 A9 A13 A21
F1 F2 F3 F4
F7 F8 F9 F10
NC A1 A4 A17
G1 G2 G3 G4
A10 A14 A22 NC
G7 G8 G9 G10
NC A0 VSS DQ1
DQ6 NC A16 NC
H2 H3 H4 H5 H6 H7 H8 H9
CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 NC
J2 J3 J4 J5 J6 J7 J8 J9
CE#1ps DQ0 DQ10 VCCf VCCps DQ12 DQ7
K3 K4 K5 K6 K7 K8
VSS
DQ8 DQ2 DQ11 NC DQ5 DQ14
L1
L5 L6
L10
NC NC NC NC
M1 M10
NC NC
Pseudo
SRAM Only
Flash Only
Shared
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (BGA). The package and/or data
integrity may be compromised if the package body is
exposed to temperatures above 150°C for prolonged
periods of time.
December 18, 2003
Am49PDL127AH/Am49PDL129AH
9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM49PDL127AH.PDF ] | |
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