PDF AM49DL640AH Data sheet ( Hoja de datos )

Número de pieza	AM49DL640AH
Descripción	Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
Fabricantes	AMD
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No Preview Available ! Am49DL640AH Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information www.DataSheet4U.com Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 26549 Revision B Amendment +1 Issue Date December 12, 2003 1 page ADVANCE INFORMATION TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations. . . . . . . . . . . . . . . . . 9 Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH ....................................................................................... 10 Table 2. Device Bus Operations—Flash Byte Mode .......................11 Flash Device Bus Operations . . . . . . . . . . . . . . . 12 Requirements for Reading Array Data ................................... 12 Writing Commands/Command Sequences ............................ 12 Accelerated Program Operation ............................................. 12 Autoselect Functions .............................................................. 12 Simultaneous Read/Write Operations with Zero Latency ....... 12 Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 13 RESET#: Hardware Reset Pin ............................................... 13 Output Disable Mode .............................................................. 13 Table 3. Am29DL640H Sector Architecture ....................................14 Table 4. Bank Address ....................................................................16 Table 5. SecSi™ Sector Addresses ...............................................16 Sector/Sector Block Protection and Unprotection .................. 17 Table 6. Am29DL640H Boot Sector/Sector Block Addresses for Protection/Unprotection ...........................................17 Write Protect (WP#) ................................................................ 18 Table 7. WP#/ACC Modes ..............................................................18 Temporary Sector Unprotect .................................................. 18 Figure 1. Temporary Sector Unprotect Operation........................... 18 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 19 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 20 Figure 3. SecSi Sector Protect Verify.............................................. 21 Hardware Data Protection ...................................................... 21 Low VCC Write Inhibit .............................................................. 21 Write Pulse “Glitch” Protection ............................................... 21 Logical Inhibit .......................................................................... 21 Power-Up Write Inhibit ............................................................ 21 Common Flash Memory Interface (CFI) . . . . . . . 21 Table 8. CFI Query Identification String .............................. 22 Table 9. System Interface String......................................................22 Table 10. Device Geometry Definition................................. 23 Table 11. Primary Vendor-Specific Extended Query........... 24 Flash Command Definitions . . . . . . . . . . . . . . . . 25 Reading Array Data ................................................................ 25 Reset Command ..................................................................... 25 Autoselect Command Sequence ............................................ 25 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 25 Word Program Command Sequence ..................................... 26 Unlock Bypass Command Sequence ..................................... 26 Figure 4. Program Operation .......................................................... 27 Chip Erase Command Sequence ........................................... 27 Sector Erase Command Sequence ........................................ 27 Erase Suspend/Erase Resume Commands ........................... 28 Figure 5. Erase Operation.............................................................. 28 Table 12. Am29DL640H Command Definitions................... 29 Flash Write Operation Status. . . . . . . . . . . . . . . . 30 DQ7: Data# Polling ................................................................. 30 Figure 6. Data# Polling Algorithm .................................................. 30 RY/BY#: Ready/Busy#............................................................ 31 DQ6: Toggle Bit I .................................................................... 31 Figure 7. Toggle Bit Algorithm........................................................ 31 DQ2: Toggle Bit II ................................................................... 32 Reading Toggle Bits DQ6/DQ2 ............................................... 32 DQ5: Exceeded Timing Limits ................................................ 32 DQ3: Sector Erase Timer ....................................................... 32 Table 13. Write Operation Status ................................................... 33 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 34 Figure 8. Maximum Negative Overshoot Waveform ...................... 34 Figure 9. Maximum Positive Overshoot Waveform........................ 34 Flash DC Characteristics . . . . . . . . . . . . . . . . . . . 35 CMOS Compatible .................................................................. 35 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 36 Figure 11. Typical ICC1 vs. Frequency ............................................ 36 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 12. Test Setup.................................................................... 38 Figure 13. Input Waveforms and Measurement Levels ................. 38 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 39 CE#1ps Timing ....................................................................... 39 Figure 14. Timing Diagram for Alternating Between Pseudo SRAM and Flash................................................ 39 Read-Only Operations ........................................................... 40 Figure 15. Read Operation Timings ............................................... 40 Hardware Reset (RESET#) .................................................... 41 Figure 16. Reset Timings ............................................................... 41 Word Configuration (CIOf) ...................................................... 42 Figure 17. CIOf Timings for Read Operations................................ 42 Figure 18. CIOf Timings for Write Operations................................ 42 Erase and Program Operations .............................................. 43 Figure 19. Program Operation Timings.......................................... 44 Figure 20. Accelerated Program Timing Diagram.......................... 44 Figure 21. Chip/Sector Erase Operation Timings .......................... 45 Figure 22. Back-to-back Read/Write Cycle Timings ...................... 46 Figure 23. Data# Polling Timings (During Embedded Algorithms). 46 Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 47 Figure 25. DQ2 vs. DQ6................................................................. 47 Temporary Sector Unprotect .................................................. 48 Figure 26. Temporary Sector Unprotect Timing Diagram .............. 48 Figure 27. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 49 Alternate CE#f Controlled Erase and Program Operations .... 50 Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings.......................................................................... 51 Pseudo SRAM AC Characteristics . . . . . . . . . . . 52 Power Up Time ....................................................................... 52 Read Cycle ............................................................................. 52 Figure 29. Pseudo SRAM Read Cycle—Address Controlled......... 52 Figure 30. Pseudo SRAM Read Cycle........................................... 53 Write Cycle ............................................................................. 54 Figure 31. Pseudo SRAM Write Cycle—WE# Control ................... 54 Figure 32. Pseudo SRAM Write Cycle—CE1#s Control ................ 55 December 12, 2003 Am49DL640AH 3 5 Page ADVANCE INFORMATION ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49DL640 A H 70 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40°C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations PROCESS TECHNOLOGY H = 130 µm floating-gate technology pSRAM DEVICE DENSITY A = 16 Mbits AMD DEVICE NUMBER/DESCRIPTION Am49DL640AH Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL640H 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD or Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations Order Number Package Marking Am49DL640AH56I M49000003J Am49DL640AH70I T, S M49000003D Am49DL640AH85I M49000003E MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. December 12, 2003 Am49DL640AH 9 11 Page

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