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PDF AM42DL6402G Data sheet ( Hoja de datos )
| Número de pieza | AM42DL6402G | |
| Descripción | Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM | |
| Fabricantes | AMD | |
| Logotipo |  |
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Am42DL6402G
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
www.DataSheet4U.com
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 26961 Revision A Amendment +1 Issue Date January 31, 2003
1 page  
PRELIMINARY
Flash Erase And Programming Performance . . . 58
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 58
Fine-pitch BGA Capacitance. . . . . . . . . . . . . . . . 58
flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 58
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 59
Figure 34. CE1#s Controlled Data Retention Mode........................ 59
Figure 35. CE2s Controlled Data Retention Mode......................... 59
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 60
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61
4
Am42DL6402G
January 31, 2003
5 Page 
PRELIMINARY
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
Operation
(Notes 1, 2)
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH
CE#f CE1#s CE2s OE# WE#
Addr.
LB#s UB#s RESET#
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
Read from Flash
HX
L
X
L L H AIN
XX
H
L/H
DOUT
DOUT
Write to Flash
HX
L
HL
AIN
XX
XL
H
(Note 4)
DIN
DIN
Standby
VCC ±
0.3 V
H
X
X
XX
L
X
X
X
VCC ±
0.3 V
H High-Z High-Z
Output Disable
HH
X
LX
L LH
H
HH
X
XL
L/H High-Z High-Z
HX
Flash Hardware Reset
X
XX
X
XX
XL
L
L/H High-Z High-Z
Sector Protect
(Note 5)
HX
SADD,
L
X
L
H
L
A6 = L,
A1 = H,
X
X
VID
A0 = L
L/H DIN X
HX
SADD,
Sector Unprotect (Note
5)
L
X
L
H
L
A6 = H,
A1 = H,
X
X
VID
(Note 6)
DIN
A0 = L
X
Temporary Sector
Unprotect
HX
X
X
XX
L
X
XX
VID
(Note 6)
DIN High-Z
Read from SRAM
Write to SRAM
LL
H L H L H AIN H L
H
LH
LL
H L H X L AIN H L
H
LH
DOUT
DOUT
X
High-Z
DOUT
DOUT High-Z
DIN DIN
X
High-Z
DIN
DIN High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN =
Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on
whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC =
VHH, all sectors will be unprotected.
10
Am42DL6402G
January 31, 2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM42DL6402G.PDF ] | |
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