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PDF AM29DS323D Data sheet ( Hoja de datos )

Número de pieza AM29DS323D
Descripción Simultaneous Operation Flash Memory
Fabricantes AMD　
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Am29DS323D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. Please contact a Spansion repre-
sentative for alternates.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 23480 Revision A Amendment 5 Issue Date October 10, 2006

1 page




AM29DS323D pdf
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .................... 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29DS323D Device Bus Operations ...............................9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation ......................................................10
Autoselect Functions .......................................................................10
Simultaneous Read/Write Operations with Zero Latency ....... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29DS323D Device Bank Divisions ...............................11
Table 3. Top Boot Sector Addresses (Am29DS32xDT) ..................12
Table 4. Secured Silicon Sector Addresses for Top Boot Devices . 13
Table 5. Bottom Boot Sector Addresses (Am29DS32xDB) ............14
Table 6. Secured Silicon Sector Addresses for Bottom Boot Devices
15
Autoselect Mode ..................................................................... 16
Table 7. Am29DS323D Autoselect Codes (High Voltage Method) 16
Sector/Sector Block Protection and Unprotection .................. 17
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................17
Table 9. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................17
Write Protect (WP#) ................................................................ 18
Temporary Sector/Sector Block Unprotect ............................. 18
Figure 1. Temporary Sector Unprotect Operation........................... 18
Figure 2. In-System Sector/Sector Block Protect
and Unprotect Algorithms................................................................ 19
Secured Silicon Sector Flash Memory Region ....................... 20
Hardware Data Protection ...................................................... 20
Low VCC Write Inhibit .....................................................................21
Write Pulse “Glitch” Protection ........................................................21
Logical Inhibit ..................................................................................21
Power-Up Write Inhibit ....................................................................21
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 10. CFI Query Identification String ........................................ 21
Table 11. System Interface String................................................... 22
Table 12. Device Geometry Definition ............................................ 22
Table 13. Primary Vendor-Specific Extended Query ...................... 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................ 24
Reset Command ..................................................................... 24
Autoselect Command Sequence ............................................ 24
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence .............................................................. 25
Byte/Word Program Command Sequence ............................. 25
Unlock Bypass Command Sequence ..............................................25
Figure 3. Program Operation .......................................................... 26
Chip Erase Command Sequence ........................................... 26
Sector Erase Command Sequence ........................................ 26
Erase Suspend/Erase Resume Commands ........................... 27
Figure 4. Erase Operation.............................................................. 27
Command Definitions ............................................................. 28
Table 14. Am29DS323D Command Definitions.............................. 28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling ................................................................. 29
Figure 5. Data# Polling Algorithm .................................................. 29
RY/BY#: Ready/Busy# ............................................................ 30
DQ6: Toggle Bit I .................................................................... 30
Figure 6. Toggle Bit Algorithm........................................................ 30
DQ2: Toggle Bit II ................................................................... 31
Reading Toggle Bits DQ6/DQ2 ............................................... 31
DQ5: Exceeded Timing Limits ................................................ 31
DQ3: Sector Erase Timer ....................................................... 31
Table 15. Write Operation Status ................................................... 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 7. Maximum Negative Overshoot Waveform ..................... 33
Figure 8. Maximum Positive Overshoot Waveform....................... 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 35
Figure 10. Typical ICC1 vs. Frequency ............................................ 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup.................................................................... 36
Table 16. Test Specifications ......................................................... 36
Figure 12. Input Waveforms and Measurement Levels ................. 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Read Operation Timings ............................................... 37
Figure 14. Reset Timings ............................................................... 38
Word/Byte Configuration (BYTE#) .......................................... 39
Figure 15. BYTE# Timings for Read Operations............................ 39
Figure 16. BYTE# Timings for Write Operations............................ 39
Erase and Program Operations .............................................. 40
Figure 17. Program Operation Timings.......................................... 41
Figure 18. Accelerated Program Timing Diagram.......................... 41
Figure 19. Chip/Sector Erase Operation Timings .......................... 42
Figure 20. Back-to-back Read/Write Cycle Timings ...................... 43
Figure 21. Data# Polling Timings (During Embedded Algorithms). 44
Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 23. DQ2 vs. DQ6................................................................. 45
Figure 24. Temporary Sector/Sector Block
Unprotect Timing Diagram ............................................................. 46
Figure 25. Sector/Sector Block Protect/Unprotect Timing Diagram 47
Figure 26. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 49
Erase And Programming Performance . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)
6 x 12 mm package ................................................................ 51
TS 048—48-Pin Standard TSOP ............................................ 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
October 10, 2006 23480A5
Am29DS323D
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AM29DS323D arduino
DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29DS323D Device Bus Operations
DQ8–DQ15
Read
Write
Operation
Standby
CE# OE# WE# RESET# WP#/ACC
L LH
H
L/H
L HL
H (Note 3)
VCC ±
0.3 V
X
X
VCC ±
0.3 V
H
Addresses
(Note 2)
AIN
AIN
X
DQ0– BYTE#
DQ7 = VIH
BYTE#
= VIL
DOUT
DIN
DOUT DQ8–DQ14 = High-Z,
DIN DQ15 = A-1
High-Z High-Z
High-Z
Output Disable
L HH
H
L/H
X High-Z High-Z High-Z
Reset
X XX
L
L/H
X High-Z High-Z High-Z
Sector Protect (Note 2)
L HL
VID
L/H
SA, A6 = L,
A1 = H, A0 = L
DIN
X
X
Sector Unprotect (Note 2)
L HL
VID
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
DIN
X
X
Temporary Sector Unprotect X X X
VID (Note 3)
AIN
DIN DIN
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 9.0–11.0 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
October 10, 2006 23480A5
Am29DS323D
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