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PDF EM6603 Data sheet ( Hoja de datos )
| Número de pieza | EM6603 | |
| Descripción | Ultra Low Power Multi I/O Microcontroller | |
| Fabricantes | EM Microelectronic | |
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EM MICROELECTRONIC - MARIN SA
EM6603
Ultra Low Power Multi I/O Microcontroller
Features
• Low Power - typical 1.8µA active mode
- typical 0.35µA standby mode
- typical 0.1µA sleep mode
@ 1.5V, 32kHz, 25 °C
• Low Voltage - 1.2 to 3.6 V
• buzzer - three tone
• ROM - 2k × 16 (Mask Programmed)
• RAM - 96 × 4 (User Read/Write)
• 2 clocks per instruction cycle
• RISC architecture
• 4 software configurable 4-bit ports
• Up to 16 inputs (4 ports)
• Up to 12 outputs (3 ports)
• Serial (Output) Write buffer - SWB
• Voltage level detection
• Analogue watchdog
• Timer watchdog
• 8 bit timer / event counter
• Internal interrupt sources (timer, event
counter, prescaler, SWB)
• External interrupt sources (portA + portC)
Description
The EM6603 is an advanced single chip low cost,
mask programmed - CMOS 4-bit microcontroller. It
contains ROM, RAM, watchdog timer, oscillation
detection circuit, combined timer / event counter,
prescaler, voltage level detector and a number of
clock functions. Its low voltage and low power
operation make it the most suitable controller for
battery, stand alone and mobile equipment. The
EM66XX series is manufactured using EM
Microelectronic’s Advanced Low Power CMOS
Process.
Typical Applications
• sensor interfaces
• domestic appliances
• security systems
• bicycle computers
• automotive controls
• TV & audio remote controls
• measurement equipment
• R/F and IR. control
Figure 1.Architecture
Figure 2.Pin Configuration
Copyright 2002, EM Microelectronic-Marin SA
1
03/02 REV. G/439
www.emmicroelectronic.com
1 page  
EM6603
1 Operating modes
The EM6603 has two low power dissipation modes:
STANDBY and SLEEP. Figure 4 is a transition
diagram for these modes.
Figure 4.Mode Transition diagram
1.1 STANDBY Mode
Executing a HALT instruction puts the EM6603 into
STANDBY mode. The voltage regulator, oscillator,
Watchdog timer, interrupts and timer/event counter are
operating. However, the CPU stops since the clock
related to instruction execution stops. Registers, RAM,
and I/O pins retain their states prior to STANDBY
mode. STANDBY is cancelled by a RESET or an
Interrupt request if enabled.
1.2 SLEEP MODE
Writing to the SLEEP* bit in the IntRq* register puts
the EM6603 in SLEEP mode. The oscillator stops and
most functions of the EM6603 are inactive. To be able
to write the SLEEP bit, the SLmask bit must first be
set to 1. In SLEEP mode only the voltage regulator
and RESET input are active. The RAM data integrity is
maintained. SLEEP mode may be cancelled only by a
RESET at the terminal pin of the EM6603. The RESET
must be high for at least 2µsec.
Table 2 : shows the state of the EM6603 functions in
STANDBY and SLEEP modes.
Table 2.StandBy and Sleep Activities
FUNCTION
STANDBY SLEEP
Oscillator
Active
Stopped
Instruction Execution Stopped Stopped
Registers and Flags Retained Reset
Interrupt Functions Active
Stopped
RAM
Retained Retained
Timer/Counter
Active
Stopped
Watchdog
Active
Stopped
I/O pins
Active
High-Z or
Retained
Supply VLD
Stopped Stopped
Reset pin
Active
Active
Due to the cold start characteristics of the oscillator, waking up from SLEEP mode may take some time to
guarantee that the oscillator has started correctly. During this time the circuit is in RESET and the strobe output
STB/RST is high. Waking up from SLEEP mode clears the SLEEP flag but not the SLmask bit. By reading
SLmask one can therefore determine if the EM6603 was powered up (SLmask = 0), or woken from SLEEP mode
(SLmask = 1).
2 Power Supply
The EM6603 is supplied by a single external power supply between Vdd and Vss, the circuit reference being at
Vss (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the oscillator and internal
logic. Output drivers are supplied directly from the external supply Vdd. A typical connection configuration is shown
in Figure 3.
For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg
For Vdd>1.8V then the configuration shown in Fig.3 should be used.
*registers are marked in bold and underlined like
*Bits/Flags in registers are marked in bold only like
IntRq
SLEEP
Copyright 2002, EM Microelectronic-Marin SA
5
03/02 REV. G/439
www.emmicroelectronic.com
5 Page 
EM6603
6.3 PortB
The EM6603 has one four bit general purpose I/O port. Each bit PB(0:3) can be separately configured by
software to be either input or output by writing to the corresponding bit of the CIOPortB control register. The
PortB register is used to read data when in input mode and to write data when in output mode. On each
terminal Pull-Up/Down resistor can be selected by metal option which are active only when selected as input.
Input mode is set by writing 0 to the corresponding bit in the CIOPortB register. This results in a high
impedance state with the status of the pin being read from register PortB. Output mode is set by writing 1 to the
corresponding bit in the CIOPortB register. Consequently the output terminal follows the status of the bits in the
PortB register. At initial RESET the CIOPortB register is set to 0, thus setting the port to an input. Additionally,
PB0 can also be used as a three tone buzzer output. For details see section 7.
6.4 PortB registers
Table 14.PortB input status register - PortB
Bit Name
3 PB3
2 PB2
1 PB1
0 PB0
Reset
-
-
-
-
R/W
R/W
R /W
R/W
R /W
Description
PB3 I/O data
PB2 I/O data
PB1 I/O data
PB0 I/O data
Table 15.PortB Input/Output control register - CIOportB
Bit Name
Reset
R/W
3
CIOPB3
0
R/W
2
CIOPB2
0
R/W
1
CIOPB1
0
R/W
0
CIOPB0
0
R/W
Description
PB3 Input/Output select
PB2 Input/Output select
PB1 Input/Output select
PB0 Input/Output select
Figure 7.Port B
If metal mask option 5Y (Input blocked when Output) is used and the port is declared as the Output (CIOPortB
= 1111b) the real port information cannot be read directly. In this case no direct logic operations (like AND
PortB) on Output ports are possible. This logic operation can be made with an image of the Port saved in the
RAM which we store after on the output port. This is valid for PortB, PortC and PortD when declared as output
and the metal Option 5Y is used. In the case of metal option 5N selected direct logic operations on output ports
are possible.
If metal mask option 6Y (Output Hi-Z in SLEEP mode) the active Output will go Tristate when the circuit goes
into SLEEP mode. In the case of 6N output stay active also in the SLEEP mode.
Copyright 2002, EM Microelectronic-Marin SA
11
03/02 REV. G/439
www.emmicroelectronic.com
11 Page | ||
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