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PDF PLC42VA12 Data sheet ( Hoja de datos )
| Número de pieza | PLC42VA12 | |
| Descripción | CMOS programmable multi-function PLD 42 x 105 x 12 | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
DESCRIPTION
The new PLC42VA12 CMOS PLD from
Philips Semiconductors exhibits a unique
combination of the two architectural concepts
that revolutionized the PLD marketplace.
The Philips Semiconductors unique Output
Macro Cell (OMC) embodies all the
advantages and none of the disadvantages
associated with the “V” type Output Macro
Cell devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement
in the configurability and efficiency of
multi-function PLDs.
The most significant improvement in the
Output Macro Cell structure is the
implementation of the register bypass
function. Any of the 10 J-K/D registers can be
individually bypassed, thus creating a
combinatorial I/O path from the AND array to
the output pin. Unlike other “V” type devices,
the register in the PLC42VA12 Macro Cell
remains fully functional as a buried register.
Both the combinatorial I/O and buried register
have separate input paths (from the AND
array). In most V-type architectures, the
register is lost as a resource when the cell is
configured as a combinatorial I/O. This
feature provides the capability to operate the
buried register independently from the
combinatorial I/O.
The PLC42VA12 is an EPROM-based CMOS
device. Designs can be generated using
Philips Semiconductors SNAP PLD design
software packages or one of several other
commercially available JEDEC standard PLD
design software packages.
FEATURES
• High-speed EPROM-based CMOS
Multi-Function PLD
– Super set of 22V10, 32VX10 and
20RA10 PAL® ICs
• Two fully programmable arrays eliminate
“P-term Depletion”
– Up to 64 P-terms per OR function
• Improved Output Macro Cell Structure
– Individually programmable as:
* Registered Output with feedback
* Registered Input
* Combinatorial I/O with Buried Register
* Dedicated I/O with feedback
* Dedicated Input (combinatorial)
– Bypassed Registers are 100% functional
with separate input and feedback paths
– Individual Output Enable control
functions
* From pin or AND array
• Reprogrammable – 100% tested for
programmability
• Eleven clock sources
• Register Preload and Diagnostic Test Mode
Features
• Security fuse
APPLICATIONS
• Mealy or Moore State Machines
– Synchronous
– Asynchronous
• Multiple, independent State Machines
• 10-bit ripple cascade
• Sequence recognition
• Bus Protocol generation
• Industrial control
• A/D Scanning
PIN CONFIGURATIONS
FA and N Pack-
ages
I0/CLK 1
I1 2
I2 3
I3 4
I4 5
I5 6
I6 7
I7 8
I8 9
B0 10
B1 11
GND 12
24 VCC
23 M9
22 M8
21 M7
20 M6
19 M5
18 M4
17 M3
16 M2
15 M1
14 M0
13 I9/OE
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
A Package
I0/
I2 I1 CLK N/C VCC M9 M8
4 3 2 1 28 27 26
I3 5
25 M7
I4 6
24 M6
I5 7
23 M5
N/C 8
22 N/C
I6 9
21 M4
I7 10
20 M3
I8 11
19 M2
12 13 14 15 16 17 18
B0 B1 GND N/C I9/ M0 M1
OE
A = Plastic Leaded Chip Carrier (450mil-square)
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line with window,
Reprogrammable (300mil-wide)
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
28-Pin Plastic Leaded Chip Carrier,
One Time Programmable (450mil-wide)
ORDER CODE
PLC42VA12FA
PLC42VA12N
PLC42VA12A
DRAWING NUMBER
1478A
0410D
0401F
PAL is a registered trademark of Advanced Micro Devices, Inc.
October 22, 1993
73
853–1414 11164
1 page  
Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
RATINGS
UNIT
VCC Supply voltage
–0.5 to +7
VDC
VIN Input voltage
–0.5 to VCC +0.5
VDC
VOUT
Output voltage
–0.5 to VCC +0.5
VDC
IIN Input currents
–10 to +10
mA
IOUT
Output currents
+24 mA
Tamb
Operating temperature range
0 to +75
°C
Tstg Storage temperature range
–65 to +150
°C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal
rise ambient to
junction
150°C
75°C
75°C
AC TEST CONDITIONS
C1 C2
INPUTS
VCC +5V S1
OE
In MZ
In DUT
BM
BM MZ
CK GND
R1
R2 CL
OUTPUTS
NOTE:
C1 and C2 are to bypass VCC to GND.
Test Load Circuit
VOLTAGE WAVEFORMS
+3.0V
90%
0V
+3.0V
10%
5ns
tR tF
5ns
90%
0V
5ns
10%
5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
October 22, 1993
77
5 Page 
Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
REGISTER SELECT OPTIONS (Continued)
PR
FC
PR
PR
FROM
OR ARRAY
D
CK
FROM
AND ARRAY
Q
CLOCK
OPTIONS
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
FROM
OR ARRAY
P
J
K
FROM
AND ARRAY
FC = LOW
FC = HIGH
R
CK
CLOCK
OPTIONS
OMC
Q CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
REGISTER MODE (D or JK)
DYNAMICALLY CONTROLLABLE
FC CONTROL P-TERM
CODE
A
L or H
POLARITY OPTIONS (for Combinatorial I/O Configurations Only1)
FROM
OR ARRAY
OMC CONFIG.
OPTIONS
OUTPUT SELECT
OPTIONS
M
FROM
OR ARRAY
POLARITY
ACTIVE-HIGH (NON-INVERTING)
CODE
H4
OMC CONFIG.
OPTIONS
OUTPUT CONTROL
OPTIONS
M
POLARITY
ACTIVE-LOW (INVERTING)
CODE
L4
Polarity Options
When an OMC is configured as a
Combinatorial I/O with Buried Register, the
polarity of the combinatorial path can be
programmed as Active-High or Active-Low. A
configurable EX-OR gate provides polarity
control.
If an OMC is configured as a Registered
Output, /Q is propagated to the output pin.
Note that either Q or /Q can be fedback to
the AND array by manipulating the feedback
logic equations. (TRUE or COMPLEMENT).
CLOCK OPTIONS
REGISTER SELECT OPTIONS
FROM
OR ARRAY
TO
AND ARRAY
D (OR J) CK
(K) Q
REGISTER SELECT OPTIONS
CLK
CLK OPTIONS
EXTERNAL CLOCK
(FROM PIN 1)
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
CK CLK OPTIONS
P-TERM CLOCK
CODE
A
CODE
•
Clock Options
In the unprogrammed state, all Output Macro
Cell clock sources are connected to the
External Clock pin (I0/CLK pin 1). Each OMC
can be individually programmed such that its
P-term Clock (CKn) is enabled, thus disabling
it from the External Clock and providing
event-driven clocking capability.
This feature supports multiple state machines,
clocked at several different rates, all on one
chip, or the ability to collect large amounts of
random logic, including 10 separately clocked
flip-flops.
FROM
OR ARRAY
TO
AND ARRAY
Notes on page 87.
D (OR J) CK
(K) Q
October 22, 1993
OMC
CONFIG.
OPTIONS
OUTPUT
CONTROL
OPTIONS
83
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